CN8223
3.0 Registers
ATM Transmitter/Receiver with UTOPIA Interface
3.5 Receive Control Registers
0x15–0x1C—HDR_VALx_12, HDR_VALx_34 (Receive Header Value Register)
The Receive Header Value registers for port x (where x can be 0 to 3) are located at addresses 0x15–0x1C. The
header values direct ATM cells to each port. If an incoming ATM cell header matches the value in the header
register, the cell is directed to that port. Receive Header Mask registers further qualify ATM cell reception.
Table 3-9 defines the HDR_VALx register addresses.
Table 3-9. HDR_VALx Register Addresses
Address
Register Name
Description
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
HDR_VAL0_12
HDR_VAL0_34
HDR_VAL1_12
HDR_VAL1_34
HDR_VAL2_12
HDR_VAL2_34
HDR_VAL3_12
HDR_VAL3_34
Receive Port 0 ATM Header Value—Octets 1, 2
Receive Port 0 ATM Header Value—Octets 3, 4
Receive Port 1 ATM Header Value—Octets 1, 2
Receive Port 1 ATM Header Value—Octets 3, 4
Receive Port 2 ATM Header Value—Octets 1, 2
Receive Port 2 ATM Header Value—Octets 3, 4
Receive Port 3 ATM Header Value—Octets 1, 2
Receive Port 3 ATM Header Value—Octets 3, 4
HDR_VAL0_12, HDR_VAL1_12, HDR_VAL2_12, HDR_VAL3_12
Field
Size
Bit
Name
Description
15–8
7–0
8
8
Header Value—Octet 1
Header Value—Octet 2
Receive Port X ATM Header Match Value—Octet 1
Receive Port X ATM Header Match Value—Octet 2
HDR_VAL0_34, HDR_VAL1_34, HDR_VAL2_34, HDR_VAL3_34
Field
Size
Bit
Name
Description
15–8
7–0
8
Header Value—Octet 3
Header Value—Octet 4
Receive Port X ATM Header Match Value—Octet 3
Receive Port X ATM Header Match Value—Octet 4
8
100046C
Conexant
3-21
CONEXANT [ CONEXANT SYSTEMS, INC ]
