CN8223
3.0 Registers
ATM Transmitter/Receiver with UTOPIA Interface
3.5 Receive Control Registers
0x25, 0x26—RX_IDLE_12, RX_IDLE_34 (Receive Idle Header Registers)
The Receive Idle Header Value registers are located at addresses 0x25 and 0x26. These registers define ATM
idle cells for the cell receiver. Idle cells are counted and usually discarded.
Field
Size
Bit
Name
Description
15–8
7–0
8
8
Header Value—Octet 1
Header Value—Octet 2
Receive Port X ATM Header Match Value—Octet 1
Receive Port X ATM Header Match Value—Octet 2
Field
Size
Bit
Name
Description
15–8
7–0
8
8
Header Value—Octet 3
Header Value—Octet 4
Receive Port X ATM Header Match Value—Octet 3
Receive Port X ATM Header Match Value—Octet 4
0x27, 0x28—IDLE_MSK_12, IDLE_MSK_34 (Receive Idle Header Mask Register)
The Receive Idle Header Mask registers are located at addresses 0x27 and 0x28. These registers modify the
ATM cell screen in the RX_IDLE_12, 34 registers. Setting a bit in the Mask register causes the corresponding
bit in the received ATM idle cell header to be disregarded for screening. For example, setting IDLE_MSK_12,
bit 0 to 1, causes cells to be accepted as ATM idle cells with either 1 or 0 in the octet 2, bit 0 position.
Field
Size
Bit
Name
Description
15–8
7–0
8
8
Header Value—Octet 1
Header Value—Octet 2
Receive ATM Idle Cell Header Mask Value—Octet 1
Receive ATM Idle Cell Header Mask Valu—Octet 2
Field
Size
Bit
Name
Description
15–8
7–0
8
8
Header Value—Octet 3
Header Value—Octet 4
Receive ATM Idle Cell Header Mask Value—Octet 3
Receive ATM Idle Cell Header Mask Value—Octet 4
100046C
Conexant
3-23
CONEXANT [ CONEXANT SYSTEMS, INC ]
