CN8223
2.0 Functional Description
ATM Transmitter/Receiver with UTOPIA Interface
2.4 Status and Alarms
2.4 Status and Alarms
The CN8223 automatically receives and generates alarms.
2.4.1 Status and Counter Interrupts
The status interrupt pin STAT_INT can be programmed to provide an interrupt on
any occurrence in the LINE_STATUS register [0x38]. Each of these signals
generates a receive status interrupt if the corresponding interrupt is enabled in the
EN_LINE_INT register [0x2D]. To determine if an interrupt is caused by a PHY
status event, the LINE_STATUS register is read. This clears the interrupts in that
register.
Two types of interrupts are provided: error and alarm. Error signals cause an
interrupt on each occurrence of an error condition. Error signals are bits 9–13 in
the LINE_STATUS register. Alarm signals provide an interrupt on change of
state. All other indications in LINE_STATUS are alarm indications.
Interrupt status bits for the line/PHY counter overflows are located in the
OVFL_STATUS register [0x3A]. The enables for these interrupts are in
EN_OVFL_INT [0x2F]. All counters are 16 bits. If a counter is set to interrupt, it
rolls over to zero when it exceeds its maximum value. If a counter is not set to
interrupt, it saturates at its maximum value of 65,535 and ignores further events.
To determine if an interrupt has been caused by a counter, the microprocessor
reads the OVFL_STATUS register.
If the interrupt for a particular counter is not set, the counter saturates at a
value of 65,535 and stays at that value until read. If Enable One-Second Latching
of Line Counters [bit 13 in CONFIG_1 [0x00] is set, then at each one-second
interval defined by the input ONESECI, the current counter value is latched for
the following one-second interval, and the counter is cleared. If the counter is
again read in that one-second interval, the current value of the counter is read and
then cleared.
The LCV counter [0x40] is always latched (and the counter cleared) by the
ONESECI input regardless of the setting of Enable One-Second Latching of Line
Counters. When this counter is read, the latched value is presented and then
cleared. Subsequent reads prior to the next ONESECI latching event produce a
value of zero.
100046C
Conexant
2-19
CONEXANT [ CONEXANT SYSTEMS, INC ]
