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CN8223 参数 Datasheet PDF下载

CN8223图片预览
型号: CN8223
PDF下载: 下载PDF文件 查看货源
内容描述: ATM发射器/接收器与UTOPIA接口 [ATM Transmitter/Receiver with UTOPIA Interface]
分类和应用: 异步传输模式ATM
文件页数/大小: 161 页 / 1722 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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2.0 Functional Description  
CN8223  
2.5 Parallel Line Interface  
ATM Transmitter/Receiver with UTOPIA Interface  
2.5 Parallel Line Interface  
The CN8223 has a parallel line interface consisting of TXOUT[8:0] and  
RXOUT[8:0]. These octet ports allow interfacing of external framers or other  
devices that use parallel data. Table 2-1, illustrates the architecture of this parallel  
interface. Also, this interface can be used for the Advanced Micro Devices TAXI  
interface chipset.  
2.5.1 TAXI Interface  
The parallel port of the CN8223 can be configured to interface directly with  
AMDs TAXI transmit/receive chipset. To enable this mode, set the following  
values in each of these registers:  
CONFIG_1 (0x00): Set the 8 LSBs to 0xE0.  
CONFIG_3 (0x02): Set Enable HEC Coset (bit 0) and Invert RX Clock  
(bit 8) high.  
CONFIG_4 (0x29): Set Enable TAXI Interface (bit 3) high.  
The transmit interface logic automatically generates the signals needed by the  
TAXI transmitter to insert JK sync and TT start-of-cell symbols before each  
transmitted data cell of 53 octets. When no transmit port is active, the transmitter  
sends continuous JK sync symbols.  
The receiver interface logic detects the TT start-of-cell command and  
synchronizes its cell circuitry to receive and process the 53-octet cell data. The  
receiver ignores all incoming JK sync signals while awaiting the reception of the  
TT symbol. The receiver is not clocked on any command or data octet if the  
violation indication is present on RXIN[8]. None of the indications in the  
LINE_STATUS register [0x38] are valid in TAXI mode except for One Second  
Count. Any other indications should be ignored. Violations will be counted in  
Line Counter 2. All cell status and cell event counters operate as in other modes.  
In TAXI mode, the capability to shut down the output of cells to the FIFO  
interface is lost because of the use of the RCV_HLD pin. In this mode, the control  
bits in CELL_VAL or external logic using the VLTN signal must be employed for  
this function.  
NOTE: Source and line loopbacks are not functional in TAXI mode due to the  
asymmetry between the transmit and receive control lines.  
2-22  
Conexant  
100046C