4.0 Mechanical/Electrical Specifications
CN8330
4.1 Timing Requirements
DS3/E3 Framer with 52 Mbps HDLC Controller
Table 4-1. Microprocessor Interface Timing (2 of 2)
Symbol
Parameter
Min.
Typical
Max.
Units
tclcl
tds
ALE Low to RD*/WR* Low
10
—
—
ns
Data Stable Before WR* High
Data Hold after WR* High
25
10
—
—
—
—
—
—
—
—
ns
ns
ns
ns
tdh
tsh
—
Address/Select Hold after RD*/WR* Low
Controller Port Cycle Time
110
154
NOTE(S):
(1)
T
cyc = Period of clock connected to the DS3CKI pin.
(2)
The external address/data bus capacitance will increase the data hold time if the bus remains undriven.
Figure 4-1. Microprocessor Interface Timing
CS
t
adwrh
t
sh
t
t
adrdl
wrw
RD*/WR*
t
rdd
AD[7:0]
t
ah
t
t
dh
as
t
ds
t
clcl
t
rdh
t
ALE
t
cale
rwa
4-2
Conexant
100441E
CONEXANT [ CONEXANT SYSTEMS, INC ]
