CN8330
4.0 Mechanical/Electrical Specifications
DS3/E3 Framer with 52 Mbps HDLC Controller
4.1 Timing Requirements
Figure 4-2 and Tables 4-2 through Table 4-4 illustrate the clock and data
relationships for all output and input signals. Propagation delays for the output
signals are listed below. The output signal timings are relative to the listed edge of
the clock. Clock outputs derived from clock inputs are listed with the edge as
both. This means that the delay number given applies for either edge. Input
signals should have setup and hold times with respect to the listed edge of the
given input clock. All times are listed in nanoseconds and are measured with
30 pF loading on the output pins.
Table 4-2. Clock Timing Requirements
Typical
(44.736 MHz)
Typical
(34.368 MHz)
Timing Requirements
Clock
Min.
Units
RXCKI, DS3CKI, TXCKI
RXCKI, DS3CKI, TXCKI
RXCKI, DS3CKI, TXCKI
5.0
5.0
11.2
11.2
22.4
14.55
14.55
29.1
ns
ns
ns
Low Pulse Width - ρwl
High Pulse Width - ρwh
Cycle Time - tcyc
19.0
Cycle Time
—
—
8 RXCKI
ns
ns
ns
Low Pulse Width
High Pulse Width
RXBCK
RXBCK
6 RXCKI
2 RXCKI
—
—
—
—
Figure 4-2. Output and Input Signal Timing
p
wl
p
wh
Input
Clock
Clock
Output
Signal
Input
Signal
t
su
t
t
hd
pd
100441E
Conexant
4-3
CONEXANT [ CONEXANT SYSTEMS, INC ]
