1.0 Functional Description
CX25870/871
1.3 Device Description
Flicker-Free Video Encoder with Ultrascale Technology
1.3.32 Buffered Crystal Clock Output
The buffered crystal clock output (XTL_BFO) pin provides a buffered output
(0 V to 3.3 V peak-peak) of whatever frequency is found between the CX25870’s
XTALIN and XTALOUT pins. This signal can then be used as a much more
accurate input clock to the graphics controller because controllers typically utilize
clock sources with errors between 75–150 ppm. This implementation ultimately
results in better VGA picture quality because the clock driving the data master is
within the same tolerance (i.e., 25 ppm) as the TV Out encoder. This can also lead
to a considerable savings in cost, component count, and PC board space because
the crystal attached to the data master has been completely eliminated.
On power-up, the encoder will transmit a 0 to 3.3 V signal at a frequency equal
to the frequency of the crystal found between the XTALIN and XTALOUT ports.
The tolerance of the XTL_BFO signal will match the tolerance found within the
encoder’s crystal. The CX25870 was designed to expect a 13.500 MHz 25 ppm
crystal. As a result, all the PLL_INT and PLL_FRACT register values found
within each CX25870 autoconfiguration mode possess this set of default values.
The CX25870 does have the flexibility to support an alternate 14.31818 MHz
crystal with a tolerance of 25 ppm. To switch the encoder to operate with this
crystal frequency, install an appropriate crystal and crystal circuit between the
XTALIN and XTALOUT ports and set the 14318_XTAL bit to 1. Enabling this
bit translates the 13.500 MHz-dependent auto configuration registers to their new
14.31818 MHz settings.
For CX25870 designs, a small (e.g., 33 Ω) series resistor should be added to
XTL_BFO, as close as possible to the signal source device. This reduces
overshoot and undershoot on this signal as it changes states. The buffered crystal
clock output pin should be floated if not used. Disabling the XTL_BFO pin is
possible through the XTL_BFO_DIS bit.
1.3.33 Noninterlaced Output
When the CX25870/871 is programmed for noninterlaced video out via the
NI_OUT bit, it always transmits the odd field. The FIELD pin will continue to
change state on the leading edge of the analog vertical sync. A 30 Hz offset
should be subtracted from the color subcarrier frequency while in NTSC mode so
that the color subcarrier phase is inverted from field to field. The transition from
interlaced to noninterlaced in master interface occurs during odd fields to prevent
synchronization disturbance.
NOTE: Consumer VCRs can record noninterlaced video with minor noise
artifacts, but special effects (e.g., scan >2x) may not function properly.
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Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
