1.0 Functional Description
CX25870/871
1.3 Device Description
Flicker-Free Video Encoder with Ultrascale Technology
1.3.35 Wide Screen Signaling (WSS)
The CX25870/871 supports the WSS methods outlined in the EIAJ CPR-1204
and ITU-R BT.1119 standards. Three serial interface registers control WSS data
insertion. For 525 line NTSC systems, two bits enable the insertion of the WSS
bit data on lines 20 and 283. The EWSSF1 register bit controls line 20 and
EWSSF2 controls line 283. Twenty bits are used to insert the 14 bits of payload,
plus six bits of CRC data. CRC data is not computed and must be inserted by the
user.
For 625 line PAL and SECAM systems, WSS data insertion is only specified
for line 23. In this case, the EWSSF1 register enables WSS data insertion on line
23 and EWSSF2 is ignored. Only 14 bits of payload are specified for 625 line
PAL and SECAM systems. No CRC is generated, therefore bits WSSDAT[20:15]
are ignored in these systems.
WSSINC[19:0] specifies the incremental value of the PQ ratio counter to
generate the desired WSS waveform. The increment value is found by:
525 line:
WSSINC[19:0] = 220 / (2.234*10-6*Fclk)
625 line:
WSSINC[19:0] = 220 / (200*10-9*Fclk
)
where:Fclk = CLKI frequency = CLKO frequency.
Figure 1-23 illustrates a typical WSS signal, where WSSDAT[14:1] = 0x00.
NOTE: WSS uses biphase coding of its data bits. The amplitude of the WSS pulses
is 500 mV above black when high and black when low. For further WSS
details, see specification ETS 300294 or ITU-R BT.1119.
Figure 1-23. Typical WSS Analog Waveform (NTSC)
0.5 V
0.0 V
Run-In
5.86 µs
(NTSC)
Bit 14
Bit 1
Start
Code
14 Data Bits
NTSC: Field 1, Line 20
Field 2, Line 20
Field 1, Line 23
PAL:
1-58
Conexant
100381B