2.0 Circuit Description
CX28394/28395/28398
2.2 Receiver
Quad/x16/Octal—T1/E1/J1 Framers
2.2.3.1 Frame Bit Error
Counter
The 12-bit Framing Bit Error Counter [FERR; addr 050 and 051] increments
every time a receive Ft, Fs, T1DM, FPS, or FAS error is detected. Fs (T1) and
NFAS (E1) errors can be included in the FERR count by setting FS_NFAS in
Receive Alarm Signal Configuration [RALM; addr 045]. An interrupt is available
to indicate that the FERR counter overflowed in the Counter Overflow Interrupt
Status register [ISR4; addr 007].
2.2.3.2 CRC Error
Counter
The 10-bit Cyclic Redundancy Check Error Counter [CERR; addr 052 and 053]
increments each time a receive CRC4 (E1) or CRC6 (T1) error is detected. An
interrupt is available to indicate that CERR counter overflowed in ISR4.
2.2.3.3 LCV Error
Counter
The 16-bit Line Code Violation Error Counter [LCV; addr 054 and 055]
increments each time a receive Bipolar Violation (BPV)—not including line
coding—is detected. The LCV count can include EXZ if EXZ_LCV in the
Receive Alarm Signal Configuration register [RALM; addr 045] is set. EXZ can
be configured [RZCS; addr 040] to be 8 or 16 successive zeros, following a one.
An interrupt is available to indicate that the LCV counter overflowed in ISR4.
2.2.3.4 FEBE Counter
The 10-bit Far End Block Error (FEBE) counter [FEBE; addr 056 and 057]
increments every time the RCVR encounters an E1 far-end block error. An
interrupt is available to indicate that the FEBE counter overflowed in ISR4.
2.2.4 Error Monitor
The following signal errors are detected in the RCVR:
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Frame Bit Error (FERR)
MFAS Error (MERR)
CAS Error (SERR)
CRC Error (CERR)
Pulse Density Violation (PDV)
Each error type has an interrupt enable bit that enables an interrupt to occur
marking the event, and an interrupt register bit that is read by the interrupt service
routine to determine which event caused the interrupt. All error status registers
are reset on read unless the LATCH_ERR bit is set in the Alarm/Error/Counter
Latch Configuration register [LATCH; addr 046]. LATCH_ERR enables the
one-second latching of alarms coincident with the one-second timer interrupt
[ISR6; addr 005]. With LATCH_ERR enabled, any error detected during the one
second interval is latched and held during the following one-second interval.
LATCH_ERR allows the processor to gather error statistics based on the
one-second interval.
2.2.4.1 Frame Bit Error
FERR is reported for the receive direction in the Error Interrupt Status register
[ISR5; addr 006] and for the transmit direction in Pattern Interrupt Status
[ISR0; addr 00B]. FERR indicates that one or more Ft/Fs/FPS frame-bit errors or
FAS-pattern errors occurred since the last time the interrupt status was read. The
FERR type is determined by the receive framer’s configuration [CR0; address 001].
2-6
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
