CX28394/28395/28398
2.0 Circuit Description
Quad/x16/Octal—T1/E1/J1 Framers
2.2 Receiver
2.2.4.2 MFAS Error
2.2.4.3 CAS Error
2.2.4.4 CRC Error
When CRC4 framing is enabled, MERR is reported for the receive direction in the
Error Interrupt Status register [ISR5; addr 006] and for the transmit direction in
Pattern Interrupt Status [ISR0; addr 00B]. MERR is applicable only in E1 mode,
and indicates that one or more MFAS pattern errors occurred since the interrupt
status was last read.
When CAS framing is enabled, SERR is reported for the receive direction in the
Error Interrupt Status register [ISR5; addr 006] and for the transmit direction in
Pattern Interrupt Status [ISR0; addr 00B]. SERR is only applicable in E1 mode,
and indicates that one or more errors were received in the TS16 Multiframe
Alignment Signal (MAS) since the interrupt status was last read.
CERR is reported for the receive direction in the Error Interrupt Status register
[ISR5; addr 006] and for the transmit direction in Pattern Interrupt Status
[ISR0; addr 00B]. CERR is only applicable in T1 ESF and E1 MFAS modes, and
indicates that one or more bit errors were found in the CRC4/CRC6 pattern block
since the interrupt status was last read.
2.2.4.5 Pulse Density
Violation
PDV is reported when the receive signal does not meet the pulse density
requirements of ANSI T1.403-1995 (Section 5.6). A PDV is declared when more
than 15 consecutive zeros or the average ones density falls below 12.5%. RPDV is
reported for the receive direction in the Alarm 1 Interrupt Status register
[ISR7; addr 004].
2.2.5 Alarm Monitor
The following signal alarms are detected in the RCVR:
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Loss Of Frame (LOF)
Loss Of Signal (LOS)
Receive Analog Loss Of Signal (RALOS)
Alarm Indication Signal (AIS)
Remote Alarm Indication (RAI) or Yellow Alarm (YEL)
Multiframe Yellow Alarm (MYEL)
Severely Errored Frame (SEF)
Change Of Frame Alignment (COFA)
Multiframe AIS (MAIS)
Each alarm has the following: a status register bit that reports the real-time
status of the event; an interrupt enable bit that enables an interrupt to mark the
event; and an interrupt register bit read by the interrupt service routine to identify
the event that caused the interrupt. All alarm status registers are reset on read
unless the LATCH_ALM bit is set in the Alarm/Error/Counter Latch
Configuration register [LATCH; addr 046]. LATCH_ALM enables the
one-second latching of alarms coincident with the one-second timer interrupt
[ISR6; addr 005]. With LATCH_ALM enabled, any alarm detected during the
one-second interval is latched and held during the following one-second interval.
100054E
Conexant
2-7
CONEXANT [ CONEXANT SYSTEMS, INC ]
