2.0 Circuit Description
CX28394/28395/28398
2.3 System Bus
Quad/x16/Octal—T1/E1/J1 Framers
2.3.4.1 Timebase
The RSB timebase synchronizes RFSYNC, RMSYNC, and RINDO with the
Receive System Bus Clock (RSBCKI). The RSBCK can be slaved to two
different clock sources: Receive System Bus Clock Input (RSBCKI), or Transmit
System Bus Clock Input (TSBCKI). The RSB clock selection is made through the
Clock Input Mux register [CMUX; addr 01A]. The system bus clock can also be
configured to run at twice the data rate by setting the X2CLK bit in the System
Bus Interface Configuration register [SBI_CR; addr 0D0].
In Non-Multiplexed mode, the RFSYNC/RMSYNC dual function pin is
configured for either RFSYNC or RMSYNC using the RMSYNC_EN register bit
[PIO; addr 018]. RFSYNC and RMSYNC can be configured as inputs or outputs
[PIO; addr 018]. RFSYNC and RMSYNC should be configured as inputs when
the RSB timebase is slaved to the system bus [SBI_OE; addr 0D0]. RFSYNC and
RMSYNC should be configured as outputs when the RSB timebase is master of
the system bus. RFSYNC and RMSYNC can be also configured as rising or
falling edge outputs [RSB_CR; addr 0D1]. In addition to having RFSYNC and
RMSYNC active on the frame boundary, a programmable offset is available to
select the time slot and bit offset in the frame. See the Receive System Bus Sync
Time Slot Offset [RSYNC_TS; addr 0D3] and the Receive System Bus Sync Bit
Offset [RSYNC_BIT; addr 0D2].
2.3.4.2 Slip Buffer
The 64-byte Receive PCM Slip Buffer [RSLIP; addr 1C0 to 1FF] resynchronizes
the Receiver Clock (RCKI) and data (RNRZ), to the Receive System Bus Clock
(RSBCK) and data (RPCMO). RSLIP acts like an elastic store by clocking RNRZ
data in with RCKI and clocking PCM data out on RPCMO with RSBCK.
If the system bus rate is greater than the line rate (i.e., T1 line rate and E1
system bus rate), there will be a mismatched number of time slots. The mapping
of line rate time slots to system bus time slots is done by time slot assignments
with the ASSIGN bit in the System Bus Per-Channel Control register [SBC0 to
SBC31; addr 0E0 to 0FF]. ASSIGN selects which system bus time slots are used
to transport line rate time slots. Time slot mapping is done by mapping the first
line rate time slot to the first assigned system bus time slot. For example, T1 to E1
mapping might make every fourth time slot unassigned (i.e., 3, 7, 11, 15, 19, 23,
27, 31); see Figure 2-13. This distribution of unassigned time slots averages out
the idle time slots and optimizes the use of the slip buffer.
2-28
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
