2.0 Circuit Description
CX28394/28395/28398
2.3 System Bus
Quad/x16/Octal—T1/E1/J1 Framers
64-Bit Elastic
In 64-bit Elastic mode, the slip buffer total depth is 64 bits, and the initial
throughput delay is 32 bits, one-half of the total depth. Similar to Normal mode,
Elastic mode allows the system bus to operate at any of the programmable rates,
independent of the line rate. The advantage of this mode over the Normal mode is
that throughput delay is reduced from one frame to an average of 32 bits, and the
output multiframe always retains its alignment with respect to the output data.
The disadvantage of this mode is handling the full and empty buffer conditions. In
Elastic mode, an empty or full buffer condition causes an Uncontrolled Slip
(USLIP). Unlike an FSLIP, a USLIP is of unknown size within the range of 1 to
256 bits of data. The USLIP status is reported in SSTAT.
Two-Frame Short
The Two-Frame Short mode combines the depth of the Normal mode with the
throughput delay of the Elastic mode. The Two-Frame Short mode begins in the
Elastic mode with a 32-bit initial throughput delay, and switches to the Normal
mode when the buffer becomes empty or full; thereafter the Two-Frame Short and
normal mode perform identically. If the slip buffer is full (two frames) in the
Two-Frame Short mode, an FSLIP is reported, after which the slip buffer and
Two-Frame mode perform identically.
Bypass
In Bypass mode, data is immediately clocked through RSLIP from the RCVR
to RSB, and RCKI internally replaces the system bus clock.
2.3.4.3 Signaling Buffer
The 32-byte Receive Signaling Buffer [RSIG; addr 1A0 to 1BF] stores a single
multiframe of signaling data. Each byte offset into RSIG contains signaling data
for a different time slot: offset 0 stores TS0 signaling data, offset 1 stores TS1
signaling data and so on. The signaling data is stored in the least significant 4 bits
of RSIG. The output signaling data is stored in the most significant 4 bits of
RSIG. Similar to RSLIP, the RSIG buffer has read/write processor access to read
or overwrite signaling information. RMSYNC extracts robbed-bit signaling from
RSIG onto RPCMO; RFSYNC extracts ABCD signaling from RSIG onto
RSIGO.
The RSIG buffer has the following configurable features: transparent,
robbed-bit signaling; signaling freeze; debounce signaling; and unicode
detection. Each feature is available in the Receive Signaling Configuration
register [RSIG; addr 0D7]. See the registers section for more details.
2-30
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
