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CY2292F 参数 Datasheet PDF下载

CY2292F图片预览
型号: CY2292F
PDF下载: 下载PDF文件 查看货源
内容描述: 三锁相环通用的EPROM可编程时钟发生器 [Three-PLL General-Purpose EPROM Programmable Clock Generator]
分类和应用: 晶体时钟发生器微控制器和处理器外围集成电路光电二极管可编程只读存储器电动程控只读存储器
文件页数/大小: 11 页 / 191 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY2292
Switching Characteristics, Industrial 5.0V
Parameter
t
1
Name
Output Period
Description
Clock output range, 5V
operation
CY2292I
CY2292FI
Output Duty
Cycle
[11]
Duty cycle for outputs, defined as t
2
÷
t
1[12]
f
OUT
> 66 MHz
Duty cycle for outputs, defined as t
2
÷
t
1[12]
f
OUT
< 66 MHz
t
3
t
4
t
5
t
6
t
7
t
8
t
9A
t
9B
t
9C
t
9D
t
10A
t
10B
Rise Time
Fall Time
Output Disable
Time
Output Enable
Time
Skew
CPUCLK Slew
Clock Jitter
[14]
Clock Jitter
[14]
Clock Jitter
[14]
Clock Jitter
[14]
Lock Time for
UPLL and SPLL
Slew Limits
Output clock rise time
[13]
Output clock fall time
[13]
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related
outputs
[3, 12, 14]
Frequency transition rate
Peak-to-peak period jitter (t
9A
max. – t
9A
min.), %
of clock period (f
OUT
< 4 MHz)
Peak-to-peak period jitter (t
9B
max. – t
9B
min.) (4
MHz < f
OUT
< 16 MHz)
Peak-to-peak period jitter (16 MHz < f
OUT
< 50 MHz)
Peak-to-peak period jitter (f
OUT
> 50 MHz)
Lock Time from Power-up
CPU PLL Slew Limits
CY2292I
CY2292FI
20
20
1.0
< 0.5
< 0.7
< 400
< 250
<25
<0.25
Min.
11.1
(90 MHz)
12.5
(80 MHz)
40%
45%
50%
50%
3
2.5
10
10
< 0.25
Typ.
Max.
13000
(76.923 kHz)
13000
(76.923 kHz)
60%
55%
5
4
15
15
0.5
20.0
1
1
500
350
50
1
90
80
ns
ns
ns
ns
ns
MHz/
ms
%
ns
ps
ps
ms
ms
MHz
MHz
Unit
ns
ns
Lock Time for CPLL Lock Time from Power-up
Switching Characteristics, Industrial 3.3V
Parameter
t
1
Name
Output Period
Description
Clock output range, 3.3V CY2292I
operation
CY2292FI
Output Duty
Cycle
[11]
Duty cycle for outputs, defined as t
2
÷
t
1[12]
f
OUT
> 66 MHz
Duty cycle for outputs, defined as t
2
÷
t
1[12]
f
OUT
< 66 MHz
t
3
t
4
t
5
t
6
t
7
t
8
Rise Time
Fall Time
Output Disable
Time
Output Enable
Time
Skew
CPUCLK Slew
Output clock rise time
[13]
Output clock fall
time
[13]
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related
outputs
[3, 12, 14]
Frequency transition rate
1.0
Min.
15
(66.6 MHz)
16.66
(60 MHz)
40%
45%
50%
50%
3
2.5
10
10
< 0.25
Typ.
Max.
13000
(76.923 kHz)
13000
(76.923 kHz)
60%
55%
5
4
15
15
0.5
20.0
ns
ns
ns
ns
ns
MHz/ms
Unit
ns
ns
Document #: 38-07449 Rev. *C
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