CY2292
Switching Characteristics, Commercial 5.0V
(continued)
Parameter
t
9A
t
9B
t
9C
t
9D
t
10A
t
10B
Name
Clock Jitter
[14]
Clock Jitter
[14]
Clock Jitter
[14]
Clock Jitter
[14]
Lock Time for CPLL
Description
Peak-to-peak period jitter (t
9A
max. – t
9A
min.), % of clock period (f
OUT
< 4 MHz)
Peak-to-peak period jitter (t
9B
max. – t
9B
min.)
(4 MHz < f
OUT
< 16 MHz)
Peak-to-peak period jitter (16 MHz < f
OUT
<
50 MHz)
Peak-to-peak period jitter (f
OUT
> 50 MHz)
Lock Time from Power-up
Min.
Typ.
<0.5
<0.7
Max.
1
1
Unit
%
ns
<400
<250
<25
<0.25
500
350
50
1
100
90
ps
ps
ms
ms
MHz
MHz
Lock Time for UPLL and Lock Time from Power-up
SPLL
Slew Limits
CPU PLL Slew Limits
CY2292
CY2292F
20
20
Switching Characteristics, Commercial 3.3V
Parameter
t
1
Name
Output Period
Description
Clock output range, 3.3V
operation
CY2292
CY2292F
Output Duty
Cycle
[11]
Duty cycle for outputs, defined as t
2
÷
t
1[12]
f
OUT
> 66 MHz
Duty cycle for outputs, defined as t
2
÷
t
1[12]
f
OUT
< 66 MHz
t
3
t
4
t
5
t
6
t
7
t
8
t
9A
t
9B
t
9C
t
9D
t
10A
t
10B
Rise Time
Fall Time
Output Disable
Time
Output Enable
Time
Skew
CPUCLK Slew
Clock Jitter
[14]
Clock Jitter
[14]
Clock Jitter
[14]
Clock Jitter
[14]
Lock Time for
UPLL and SPLL
Slew Limits
Output clock rise time
[13]
Output clock fall
time
[13]
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related
outputs
[3, 12, 14]
Frequency transition rate
Peak-to-peak period jitter (t
9A
max. – t
9A
min.),
% of clock period (f
OUT
< 4 MHz)
Peak-to-peak period jitter (t
9B
max. – t
9B
min.)
(4 MHz < f
OUT
< 16 MHz)
Peak-to-peak period jitter (16 MHz < f
OUT
< 50 MHz)
Peak-to-peak period jitter (f
OUT
> 50 MHz)
Lock Time from Power-up
CPU PLL Slew Limits
CY2292
CY2292F
20
20
1.0
< 0.5
< 0.7
< 400
< 250
< 25
< 0.25
Min.
12.5
(80 MHz)
15
(66.6 MHz)
40%
45%
50%
50%
3
2.5
10
10
< 0.25
Typ.
Max.
13000
(76.923 kHz)
13000
(76.923 kHz)
60%
55%
5
4
15
15
0.5
20.0
1
1
500
350
50
1
80
66.6
ns
ns
ns
ns
ns
MHz/
ms
%
ns
ps
ps
ms
ms
MHz
MHz
Unit
ns
ns
Lock Time for CPLL Lock Time from Power-up
Document #: 38-07449 Rev. *B
Page 6 of 11
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