CY2292
Switching Characteristics, Industrial 3.3V
(continued)
Parameter
t
9A
t
9B
t
9C
t
9D
t
10A
t
10B
Name
Clock Jitter
[14]
Clock Jitter
[14]
Clock Jitter
[14]
Clock Jitter
[14]
Lock Time for
CPLL
Lock Time for
UPLL and SPLL
Slew Limits
Description
Peak-to-peak period jitter (t
9A
max. – t
9A
min.),
% of clock period (f
OUT
< 4 MHz)
Peak-to-peak period jitter (t
9B
max. – t
9B
min.)
(4 MHz < f
OUT
< 16 MHz)
Peak-to-peak period jitter
(16 MHz < f
OUT
< 50 MHz)
Peak-to-peak period jitter
(f
OUT
> 50 MHz)
Lock Time from Power-up
Lock Time from Power-up
CPU PLL Slew Limits
CY2292I
CY2292FI
20
20
Min.
Typ.
< 0.5
< 0.7
< 400
< 250
< 25
< 0.25
Max.
1
1
500
350
50
1
66.6
60
Unit
%
ns
ps
ps
ms
ms
MHz
MHz
Switching Waveforms
All Outputs, Duty Cycle and Rise/Fall Time
t
1
t
2
OUTPUT
t
3
t
4
Output Three-State Timing
[4]
OE
t
5
ALL
THREE-STATE
OUTPUTS
t
6
CLK Outputs Jitter and Skew
t
9A
CLK
OUTPUT
t
7
RELATED
CLK
CPU Frequency Change
SELECT
OLD SELECT
F
old
CPU
NEW SELECT STABLE
t
8
& t
10
F
new
Document #: 38-07449 Rev. *B
Page 8 of 11
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