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CY23S05SC-1H 参数 Datasheet PDF下载

CY23S05SC-1H图片预览
型号: CY23S05SC-1H
PDF下载: 下载PDF文件 查看货源
内容描述: 低成本3.3V传播感知™零延迟缓冲器 [Low-Cost 3.3V Spread Aware⑩ Zero Delay Buffer]
分类和应用: 时钟驱动器逻辑集成电路光电二极管
文件页数/大小: 9 页 / 189 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY23S09
CY23S05
Maximum Ratings
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Input Voltage (Except REF) ............–0.5V to V
DD
+ 0.5V
DC Input Voltage REF
............................................. −0.5V
to 7V
Storage Temperature ................................. –65
°
C to +150
°
C
Max. Soldering Temperature (10 sec.) ....................... 260
°
C
Junction Temperature ................................................. 150
°
C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ........................... > 2,000V
Operating Conditions for CY23S05SC-XX and CY23S09SC-XX
Commercial Temperature Devices
[5]
Parameter
V
DD
T
A
C
L
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
Description
Min.
3.0
0
Max.
3.6
70
30
10
7
Unit
V
°C
pF
pF
pF
Electrical Characteristics for CY23S05SC-XX and CY23S09SC-XX
Commercial Temperature Devices
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
(PD mode)
I
DD
Description
Input LOW Voltage
[6]
Input HIGH Voltage
[6]
Input LOW Current
Input HIGH Current
Output LOW
Voltage
[7]
V
IN
= 0V
V
IN
= V
DD
I
OL
= 8 mA (–1)
I
OH =
12 mA (–1H)
I
OH
= –8 mA (–1)
I
OL
= –12 mA (–1H)
REF = 0 MHz
Unloaded outputs at 66.67 MHz,
SEL inputs at V
DD
2.4
12.0
32.0
2.0
50.0
100.0
0.4
Test Conditions
Min.
Max.
0.8
Unit
V
V
µA
µA
V
V
µA
mA
Output HIGH Voltage
[7]
Power-down Supply Current
Supply Current
Switching Characteristics for CY23S05SC-1 and CY23S09SC-1
Commercial Temperature Devices
[8]
Parameter
t1
Description
Output Frequency
Duty Cycle
[7]
= t
2
÷
t
1
t3
t
4
t
5
t
6
t
7
t
J
t
LOCK
Rise
Time
[7]
[7]
Test Conditions
30-pF load
10-pF load
Measured at 1.4V, F
out
= 66.67 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
Min.
10
10
40.0
Typ.
Max.
100
133.33
Unit
MHz
MHz
%
ns
ns
ps
ps
ps
ps
ms
50.0
60.0
2.50
2.50
250
Fall Time
Output-to-Output Skew
[7]
Delay, REF Rising Edge to Measured at V
DD
/2
CLKOUT Rising Edge
[7]
Device-to-Device Skew
[7]
Cycle-to-Cycle Jitter
[7]
PLL Lock Time
[7]
0
0
±350
700
200
1.0
Measured at V
DD
/2 on the CLKOUT pins
of devices
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock
presented on REF pin
Notes:
5.
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
6. REF input has a threshold voltage of V
DD
/2.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
8. All parameters specified with loaded outputs.
Document #: 38-07296 Rev. *C
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