欢迎访问ic37.com |
会员登录 免费注册
发布采购

CY23S05SC-1H 参数 Datasheet PDF下载

CY23S05SC-1H图片预览
型号: CY23S05SC-1H
PDF下载: 下载PDF文件 查看货源
内容描述: 低成本3.3V传播感知™零延迟缓冲器 [Low-Cost 3.3V Spread Aware⑩ Zero Delay Buffer]
分类和应用: 时钟驱动器逻辑集成电路光电二极管
文件页数/大小: 9 页 / 189 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
 浏览型号CY23S05SC-1H的Datasheet PDF文件第1页浏览型号CY23S05SC-1H的Datasheet PDF文件第2页浏览型号CY23S05SC-1H的Datasheet PDF文件第3页浏览型号CY23S05SC-1H的Datasheet PDF文件第4页浏览型号CY23S05SC-1H的Datasheet PDF文件第6页浏览型号CY23S05SC-1H的Datasheet PDF文件第7页浏览型号CY23S05SC-1H的Datasheet PDF文件第8页浏览型号CY23S05SC-1H的Datasheet PDF文件第9页  
CY23S09
CY23S05
Switching Characteristics for CY23S05SI-1H and CY23S09SI-1H
Industrial Temperature Devices
[8]
Parameter
t1
Description
Output Frequency
Duty Cycle
[7]
= t
2
÷
t
1
Duty Cycle
[7]
= t
2
÷
t
1
t3
t
4
t
5
t
6
t
7
t
8
t
J
t
LOCK
Rise Time
[7]
Fall Time
[7]
Test Conditions
30-pF load
10-pF load
Measured at 1.4V, F
out
= 66.67 MHz
Measured at 1.4V, F
out
<50.0 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
Min.
10
10
40.0
45.0
Typ.
Max.
100
133.33
Unit
MHz
MHz
%
%
ns
ns
ps
ps
ps
V/ns
50.0
50.0
60.0
55.0
1.50
1.50
250
Output-to-Output
Skew
[7]
All outputs equally loaded
0
0
1
Delay, REF Rising Edge to Measured at V
DD
/2
CLKOUT Rising Edge
[7]
Device-to-Device Skew
[7]
Output Slew Rate
[7]
Cycle-to-Cycle Jitter
[7]
PLL Lock Time
[7]
Measured at V
DD
/2 on the CLKOUT pins
of devices
Measured between 0.8V and 2.0V using
Test Circuit #2
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock
presented on REF pin
±350
700
200
1.0
ps
ms
Switching Waveforms
Duty Cycle Timing
t
1
t
2
1.4V
1.4V
1.4V
All Outputs Rise/Fall Time
OUTPUT
2.0V
0.8V
t
3
2.0V
0.8V
t
4
3.3V
0V
Output-Output Skew
OUTPUT
1.4V
OUTPUT
t
5
1.4V
Input-Output Propagation Delay
INPUT
V
DD
/2
OUTPUT
t
6
V
DD
/2
Document #: 38-07296 Rev. *C
Page 5 of 9