CY25811/12/14
Spread Percentage Selection
The CY25811/12/14 SSCG products provide Center-Spread, Down-Spread, and No-Spread functions. The amount of Spread
percentage is selected using 3-Level. S0 and S1 digital inputs and Spread percent values are given in
Table 3. Spread Percent Selection
XIN
(MHz)
FRSEL
S1 = 0
S0 = 0
Center
(%)
4-5
5-6
6-7
7-8
8-10
10-12
12-14
14-16
16-20
20-24
24-28
28-32
0
0
0
0
1
1
1
1
M
M
M
M
±1.4
±1.3
±1.2
±1.1
±1.4
±1.3
±1.2
±1.1
±1.4
±1.3
±1.2
±1.1
S1 = 0
S0 = M
Center
(%)
± 1.2
± 1.1
± 0.9
± 0.9
±1.2
±1.1
± 0.9
± 0.9
±1.2
±1.1
± 0.9
± 0.9
S1 = 0
S0 = 1
Center
(%)
± 0.6
± 0.5
± 0.5
± 0.4
± 0.6
± 0.5
± 0.5
± 0.4
± 0.6
± 0.5
± 0.5
± 0.4
S1 = M
S0 = 0
Center
(%)
± 0.5
± 0.4
± 0.4
± 0.3
± 0.5
± 0.4
± 0.4
± 0.3
± 0.5
± 0.4
± 0.4
± 0.3
S1 = 1
S0 = 1
Down
(%)
–3.0
–2.7
–2.5
–2.3
–3.0
–2.7
–2.5
–2.3
–3.0
–2.7
–2.5
–2.3
S1 = 1
S0 = 0
Down
(%)
–2.2
–1.9
–1.8
–1.7
–2.2
–1.9
–1.8
–1.7
–2.2
–1.9
–1.8
–1.7
S1 = M
S0 = 1
Down
(%)
–1.9
–1.7
–1.5
–1.4
–1.9
–1.7
–1.5
–1.4
–1.9
–1.7
–1.5
–1.4
S1 = 1
S0 = M
Down
(%)
–0.7
–0.6
–0.6
–0.5
–0.7
–0.6
–0.6
–0.5
–0.7
–0.6
–0.6
–0.5
S1 = M
S0 = M
No Spread
0
0
0
0
0
0
0
0
0
0
0
0
3-Level Digital Inputs
S0, S1, and FRSEL digital inputs are designed to sense 3
different logic levels designated as High “1”, Low “0”, and Middle
“M”. With this 3-Level digital input logic, the 3-Level Logic detects
nine different logic states.
S0, S1, and FRSEL pins include an on chip 20K (10K and 10K)
resistor divider. No external application resistors are needed to
implement the 3-Level logic levels as shown here:
Logic Level “0”: 3–Level logic pin connected to GND.
Logic Level “M”: 3–Level logic pin left floating (no connection).
Logic Level “1”: 3–Level logic pin connected to V
DD
.
illustrates how to implement 3–Level Logic.
Figure 2. 3–Level Logic
LOGIC
LOW (0)
S0, S1
and
FRSEL
to VSS
Modulation Rate
SSCGs use frequency modulation (FM) to distribute energy over
a specific band of frequencies. The maximum frequency of the
clock (fmax), and minimum frequency of the clock (fmin)
determine this band of frequencies. The time required to
transition from fmin to fmax and back to fmin is the period of the
Modulation Rate. The Modulation Rate of SSCG clocks are
generally referred to in terms of frequency, or:
fmod = 1/Tmod.
The input clock frequency, fin, and the internal divider determine
the Modulation Rate.
In CY25811/2/4 devices, the (Spread Spectrum) modulation
Rate, fmod, is given by the following formula:
fmod = fin/DR
LOGIC
HIGH (H)
S0, S1
and
FRSEL
to VDD
LOGIC
MIDDLE (M)
S0, S1
and
FRSEL
UNCONNECTED
Here fmod is the Modulation Rate, fin is the Input Frequency, and
DR is the Divider Ratio as given in
Note that Input
Frequency Range is set by FRSEL.
Table 4. Modulation Rate Divider Ratios
FRSEL
0
Input Frequency Range
(MHz)
4 to 8
8 to 16
16 to 32
Divider Ratio
(DR)
128
256
512
VSS
1
M
Document Number: 38-07112 Rev. *G
Page 3 of 13
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