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CY62148BLL-70SC 参数 Datasheet PDF下载

CY62148BLL-70SC图片预览
型号: CY62148BLL-70SC
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位( 512K ×8)静态RAM [4-Mbit (512K x 8) Static RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 11 页 / 336 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY62148B MoBL™
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
t
CDR[4]
t
R[9]
Description
V
CC
for Data Retention
Data Retention Current
Com’l LL
Ind’l
Operation Recovery Time
LL
No input may exceed
V
CC
+ 0.3V
V
CC
= V
DR
= 3.0V
CE > V
CC
– 0.3V
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V
Conditions
Min.
2.0
20
20
0
t
RC
Typ.
[3]
Max.
Unit
V
µA
µA
ns
ns
Chip Deselect to Data Retention Time
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
V
DR
> 2V
3.0V
t
R
Switching Waveforms
Read Cycle No.1
[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[11, 12]
ADDRESS
t
RC
CE
t
ACE
OE
t
DOE
DATA OUT
V
CC
SUPPLY
CURRENT
t
LZOE
HIGH IMPEDANCE
t
LZCE
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
50%
I
SB
HIGH
IMPEDANCE
Notes:
9. Full Device operatin requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100
µs
or stable at V
cc(min)
> 100
µs.
10. Device is continuously selected. OE, CE = V
IL
.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05039 Rev. *C
Page 5 of 11