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CY62256NLL-70PXC 参数 Datasheet PDF下载

CY62256NLL-70PXC图片预览
型号: CY62256NLL-70PXC
PDF下载: 下载PDF文件 查看货源
内容描述: 256K ( 32K × 8 )静态RAM [256K (32K × 8) Static RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 14 页 / 577 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY62256N
Switching Characteristics
Over the Operating Range
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to low Z
OE HIGH to high Z
CE LOW to low Z
CE HIGH to high Z
CE LOW to power up
CE HIGH to power down
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE LOW to high Z
WE HIGH to low Z
55
5
5
5
0
55
45
45
0
0
40
25
0
5
55
55
25
20
20
55
20
70
5
5
5
0
70
60
60
0
0
50
30
0
5
70
70
35
25
25
70
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
CY62256N-55
Min
Max
CY62256N-70
Min
Max
Unit
Write Cycle
Switching Waveforms
Figure 5. Read Cycle No. 1
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
Notes
10. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
11. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
12. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in (b) of AC Test Loads. Transition is measured
500
mV from steady-state voltage.
13. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can
terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write.
14. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
15. Device is continuously selected. OE, CE = V
IL
.
16. WE is HIGH for Read cycle.
Document Number: 001-06511 Rev. *D
Page 6 of 14