CY7C008/009
CY7C018/019
S
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Over the Operating Range
CY7C008/009
CY7C018/019
-12
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE[14]
t
DOE
t
LZOE[15, 16, 17]
t
HZOE[13, 16, 17]
t
LZCE[15, 16, 17]
t
HZCE[15, 16, 17]
t
PU[17]
t
PD[17]
t
ABE[14]
WRITE CYCLE
t
WC
t
SCE[14]
t
AW
t
HA
t
SA[14]
t
PWE
t
SD
t
HD
t
HZWE[16, 17]
t
LZWE[16, 17]
t
WDD[18]
t
DDD[18]
Write Cycle Time
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
3
25
20
12
10
10
0
0
10
10
0
10
3
30
25
15
12
12
0
0
12
10
0
10
3
45
30
20
15
15
0
0
15
15
0
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
0
12
12
3
10
0
15
15
3
10
3
10
0
20
20
3
12
8
3
10
3
12
12
12
3
15
10
3
12
15
15
3
20
12
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
-15
Max.
Min.
-20
Max.
Unit
Notes:
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OI
/I
OH
and 30-pF load capacitance.
14. To access RAM, CE=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
SCE
time.
15. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
16. Test conditions used are Load 2.
17. This parameter is guaranteed by design, but it is not production tested.
18. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
Document #: 38-06041 Rev. *C
Page 7 of 19
CYPRESS [ CYPRESS SEMICONDUCTOR ]
