CY7C024/0241
CY7C025/0251
Switching Characteristics
Over the Operating Range
[10]
(continued)
7C024/0241–15
7C025/0251–15
Parameter
BUSY TIMING
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD[17]
t
INS
t
INR
t
SOP
t
SWRD
t
SPS
t
SAA
BUSY LOW from Address
Match
BUSY HIGH from Address
Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
R/W HIGH after BUSY
(Slave)
R/W HIGH after BUSY
HIGH (Slave)
BUSY HIGH to Data Valid
INT Set Time
INT Reset Time
SEM Flag Update Pulse (OE
or SEM)
SEM Flag Write to Read
Time
SEM Flag Contention
Window
SEM Address Access Time
10
5
5
15
5
0
13
Note 17
15
15
12
10
10
25
15
15
15
15
5
0
20
Note 17
20
20
15
10
10
35
20
20
20
20
5
0
30
Note 17
25
25
20
15
15
55
20
20
20
20
5
0
40
Note 17
30
30
45
40
40
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C024/0241–25
7C025/0251–25
Min.
Max.
7C024/0241–35
7C025/0251–35
Min.
Max.
7C024/0241–55
7C025/0251–55
Min.
Max.
Unit
INTERRUPT TIMING
SEMAPHORE TIMING
Data Retention Mode
The CY7C024/0241 is designed with battery backup in mind.
Data retention voltage and supply current are guaranteed over
temperature. The following rules insure data retention:
1. Chip enable (CE) must be held HIGH during data retention, with-
in V
CC
to V
CC
– 0.2V.
2. CE must be kept between V
CC
– 0.2V and 70% of V
CC
during the power-up and power-down transitions.
3. The RAM can begin operation >t
RC
after V
CC
reaches the min-
imum operating voltage (4.5 volts).
Timing
Data Retention Mode
V
CC
4.5V
V
CC
>
2.0V
4.5V
t
RC
V
IH
CE
V
CC
to V
CC
– 0.2V
7C024–13
Parameter
ICC
DR1
Test Conditions
@ VCC
DR
= 2V
Max.
1.5
Unit
mA
Notes:
16. Test conditions used are Load 2.
17. t
BDD
is a calculated parameter and is the greater of t
WDD
–
t
PWE
(actual) or
t
DDD
–
t
SD
(actual).
18. CE = V
CC
, V
in
= GND to V
CC
, T
A
= 25°C. This parameter is guaranteed but not
tested.
Document #: 38-06035 Rev. *B
Page 8 of 20
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