CY7C1021B
CY7C10211B
Capacitance
[5]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
8
Unit
pF
pF
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
OUTPUT
THÉVENIN
EQUIVALENT
R2
255
Ω
R 481
Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
167
30 pF
1.73V
R2
255
Ω
GND
Rise Time: 1 V/ns
R 481
Ω
3.0V
ALL INPUT PULSES
90%
10%
90%
10%
Fall Time:1 V/ns
Switching Characteristics
[6]
Over the Operating Range
7C10211B-10
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
SD
t
HD
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
Data Set-Up to Write End
Data Hold from Write End
10
8
7
0
0
5
0
12
9
8
0
0
6
0
15
10
10
0
0
8
0
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[7]
OE HIGH to High Z
[7, 8]
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
0
5
0
10
5
0
6
3
5
0
12
6
0
7
0
5
3
6
0
15
7
3
10
5
0
6
3
7
10
10
3
12
6
0
7
12
12
3
15
7
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C1021B-12
Min.
Max.
7C1021B-15
Min.
Max.
Unit
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05145 Rev. *A
Page 4 of 10
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