CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms
Read Cycle No. 1
Either Port Address Access
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATAVALID
t
AA
DATA VALID
Read Cycle No. 2
Either Port CE/OE Access
CE
OE
t
LZOE
t
LZCE
DATA OUT
t
PU
I
CC
I
SB
DATA VALID
t
PD
t
ACE
t
DOE
t
HZOE
t
HZCE
Read Cycle No. 3
Read with BUSY, Master: CY7C130 and CY7C131
t
RC
ADDRESS
R
R/W
R
D
INR
ADDRESS
L
t
PS
BUSY
L
t
BLA
DOUT
L
t
WDD
t
DDD
t
BHA
t
BDD
VALID
ADDRESS MATCH
t
PWE
t
HD
VALID
ADDRESS MATCH
Notes:
19. R/W is HIGH for read cycle.
20. Device is continuously selected, CE = V
IL
and OE = V
IL
.
21. Address valid prior to or coincident with CE transition LOW.
Document #: 38-06002 Rev. *D
Page 8 of 19
CYPRESS [ CYPRESS SEMICONDUCTOR ]
