CY7C1347F
Pin Definitions
(BGA,FBGA)
Name
(100TQFP)
Name
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Description
Address Inputs used to select one of the 128K address locations.
Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
feeds the 2-bit counter.
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW.
When asserted LOW on the rising edge
of CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BW
[A:D]
and BWE).
Byte Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Clock Input.
Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK. Used in
conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH.
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
2
to select/deselect the device.
A
0,
A
1,
A
BW
A,
BW
B,
BW
C,
BW
D
GW
A
[16:0]
BW
[A:D]
GW
BWE
CLK
CE
1
CE
2
CE
3
OE
BWE
CLK
CE
1
CE
2
CE
3
OE
Input-
Output Enable, asynchronous input, active LOW.
Controls the direction of the
Asynchronous I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O
pins are three-stated, and act as input data pins. OE is masked during the first clock
of a read cycle when emerging from a deselected state.
Input-
Synchronous
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK.
When asserted, it
automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK.
When
asserted LOW, addresses presented to the device are captured in the address
registers. A
[1:0]
are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is ignored when CE
1
is deasserted
HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK.
When
asserted LOW, addresses presented to the device are captured in the address
registers. A
[1:0]
are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
ADV
ADSP
ADV
ADSP
ADSC
ADSC
Input-
Synchronous
ZZ
ZZ
Input-
ZZ “sleep” Input.
This active HIGH input places the device in a non-time-critical
Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has
to be LOW or left floating. ZZ pin has an internal pull-down.
I/O-
Synchronous
Bidirectional Data I/O lines.
As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs are
placed in a three-state condition.
Power supply inputs to the core of the device.
Ground for the core of the device.
Power supply for the I/O circuitry.
Ground for the I/O circuitry.
Selects Burst Order.
When tied to GND selects linear burst sequence. When tied
to V
DDQ
or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin has an internal pull-up.
No Connects.
DQ
A,
DQ
B
DQs
DQPs
DQ
C,
DQ
D
DQP
A,
DQP
B,
DQP
C,
DQP
D
V
DD
V
SS
V
DDQ
V
SSQ
MODE
V
DD
V
SS
V
DDQ
V
SSQ
MODE
Power Supply
Ground
I/O Power
Supply
I/O Ground
Input-
Static
NC
NC
Document #: 38-05213 Rev. *D
Page 4 of 19
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