CY7C1347F
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (T
CO
) is 2.6 ns
(250-MHz device).
The CY7C1347F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user selectable, and
is determined by sampling the MODE input. Accesses can be
initiated with either the Address Strobe from Processor
(ADSP) or the Address Strobe from Controller (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
[A:D]
) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE
1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE
1
, CE
2
, CE
3
are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE
1
is HIGH. The address presented to the address inputs (A
[16:0]
)
is stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the Output Register and onto
the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE
1
, CE
2
, CE
3
are all asserted active. The address presented
to A
[16:0]
is loaded into the Address Register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW
[A:D]
) and ADV inputs are
ignored during this first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs and DQPs inputs is written into the
corresponding address location in the RAM core. If GW is
HIGH, then the write operation is controlled by BWE and
Document #: 38-05213 Rev. *D
BW
[A:D]
signals. The CY7C1347F provides byte write
capability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BW
[A:D]
) input will selectively write to only the
desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1347F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQs and DQPs inputs. Doing so will three-state the
output drivers. As a safety precaution, DQs and DQPs are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE
1
, CE
2
, CE
3
are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW
[A:D]
) are asserted active to conduct a write to
the desired byte(s). ADSC-triggered write accesses require a
single clock cycle to complete. The address presented to
A
[16:0]
is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQs and DQPs is written
into the corresponding address location in the RAM core. If a
byte write is conducted, only the selected bytes are written.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1347F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQs and DQPs inputs. Doing so will three-state the
output drivers. As a safety precaution, DQs and DQPs are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Burst Sequences
The CY7C1347F provides a two-bit wraparound counter, fed
by A
[1:0]
, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user-selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, CE
3
, ADSP, and ADSC must
remain inactive for the duration of t
ZZREC
after the ZZ input
returns LOW.
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