CY7C1354C, CY7C1356C
Truth Table
The Truth Table for CY7C1354C and CY7C1356C follows.
Operation
Deselect cycle
Continue deselect cycle
Read cycle (begin burst)
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Write cycle (continue burst)
NOP/WRITE ABORT (begin burst)
WRITE ABORT (continue burst)
IGNORE CLOCK EDGE (stall)
SLEEP MODE
Address
Used
None
None
External
Next
External
Next
External
Next
None
Next
Current
None
CE ZZ
H
X
L
X
L
X
L
X
L
X
X
X
L
L
L
L
L
L
L
L
L
L
L
H
ADV/LD
L
H
L
H
L
H
L
H
L
H
X
X
WE
X
X
H
X
H
X
L
X
L
X
X
X
BWx
X
X
X
X
X
X
L
L
H
H
X
X
OE
X
X
L
L
H
H
X
X
X
X
X
X
CEN CLK
L
L
L
L
L
L
L
L
L
L
H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
DQ
Tri-state
Tri-state
Data out (Q)
Data out (Q)
Tri-state
Tri-state
Data in (D)
Data in (D)
Tri-state
Tri-state
-
Tri-state
Partial Write Cycle Description
The following table lists the Partial Write Cycle Description for CY7C1354C.
Function (CY7C1354C)
Read
Write– no bytes written
Write byte a –(DQ
a
and DQP
a
)
Write byte b – (DQ
b
and DQP
b
)
Write bytes b, a
Write byte c –(DQ
c
and DQP
c
)
Write bytes c, a
Write bytes c, b
Write bytes c, b, a
Write byte d –(DQ
d
and DQP
d
)
Write bytes d, a
Write bytes d, b
Write bytes d, b, a
Write bytes d, c
Write bytes d, c, a
Write bytes d, c, b
Write all bytes
WE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
BW
d
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
BW
c
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
BW
b
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
BW
a
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
Notes
2. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one bytewrite select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
3. Write is defined by WE and BWX. See Write Cycle Description table for details.
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal.
6. CEN = H inserts wait states.
7. Device will power up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tri-state when OE is
inactive or when the device is deselected, and DQs = data when OE is active.
9. Table only lists a partial listing of the byte write combinations. Any combination of BW
X
is valid. Appropriate write will be done based on which byte write is active.
Document Number: 38-05538 Rev. *K
Page 10 of 32
CYPRESS [ CYPRESS SEMICONDUCTOR ]
