FOR
FOR
enCoRe™ USB CY7C63722/23
CY7C63743
0 = The time of the most recent edge is held in the Capture Timer Data Register. That is, if multiple edges have occurred before
reading the capture timer, the time for the last one will be read (default state).
The First Edge Hold function applies globally to all four capture timers.
Bit [6:4]: Prescale Bit [2:0]
Three prescaler bits allow the capture timer clock rate to be selected among 5 choices, as shown in Table 19-1 below.
Bit [3:0]: Capture A/B, Rising/Falling Interrupt Enable
Each of the four Capture Timer registers can be individually enabled to provide interrupts.
Both Capture A events share a common interrupt request, as do the two Capture B events. In addition to the event enables,
the main Capture Interrupt Enables bit in the Global Interrupt Enable register (Section 21.0) must be set to activate a capture
interrupt.
1 = Enable interrupt
0 = Disable interrupt
Table 19-1. Capture Timer Prescalar Settings (Step size and range for FCLK = 6 MHz)
Prescale 2:0
Captured Bits
Bits 7:0 of free-running timer
Bits 8:1 of free-running timer
Bits 9:2 of free-running timer
Bits 10:3 of free-running timer
Bits 11:4 of free-running timer
LSB Step Size
1 µs
Range
256 µs
512 µs
1.024 ms
2.048 ms
4.096 ms
000
001
010
011
100
2 µs
4 µs
8 µs
16 µs
20.0
Processor Status and Control Register
Bit #
7
6
5
4
3
2
1
0
Bit Name
IRQ
Watchdog
Bus
Interrupt
Event
LVR/BOR
Suspend
Interrupt
Enable
Sense
Reserved
Run
Pending
Reset
Reset
Read/Write
Reset
R
0
R/W
1
R/W
0
R/W
1
R/W
0
R
0
-
0
R/W
1
Figure 20-1. Processor Status and Control Register (Address 0xFF)
Bit 7: IRQ Pending
When an interrupt is generated, it is registered as a pending interrupt. The interrupt will remain pending until its interrupt enable
bit is set (Figure 21-1 and Figure 21-2) and interrupts are globally enabled (Bit 2, Processor Status and Control Register). At
that point the internal interrupt handling sequence will clear the IRQ Pending bit until another interrupt is detected as pending.
This bit is only valid if the Global Interrupt Enable bit is disabled.
1 = There are pending interrupts.
0 = No pending interrupts.
Bit 6: Watchdog Reset
The Watchdog Timer Reset (WDR) occurs when the internal Watchdog timer rolls over. The timer will roll over and WDR will
occur if it is not cleared within tWATCH (see Section 26.0 for the value of tWATCH). This bit is cleared by an LVR/BOR. Note that
a watchdog reset can occur with a POR/LVR/BOR event, as discussed at the end of this section.
1 = A watchdog reset occurs.
0 = No watchdog reset
Bit 5: Bus Interrupt Event
The Bus Reset Status is set whenever the event for the USB Bus Reset or PS/2 Activity interrupt occurs. The event type (USB
or PS/2) is selected by the state of the USB-PS/2 Interrupt Mode bit in the USB Status and Control Register (see Figure 13-1).
The details on the event conditions that set this bit are given in Section 21.3. In either mode, this bit is set as soon as the event
Document #: 38-08022 Rev. **
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