CY7C64713
Logic Block Diagram
24 MHz
Ext. XTAL
High performance micro
using standard tools
with lower-power options
Address (16)
Data (8)
FX1
Address (16) / Data Bus (8)
VCC
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
I
2
C
Master
Additional IOs (24)
1.5k
connected for
enumeration
D+
USB
D–
Integrated
full speed XCVR
XCVR
CY
16 KB
RAM
Abundant IO
including two USARTS
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
ADDR (9)
GPIF
ECC
RDY (6)
CTL (6)
Smart
USB
Engine
4 kB
FIFO
8/16
Up to 96 MBytes
burst rate
Enhanced USB core
Simplifies 8051 code
‘Soft Configuration’
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Document #: 38-08039 Rev. *E
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