CY7C64713
Functional Description
EZ-USB FX1™ (CY7C64713) is a full speed, highly integrated,
USB microcontroller. By integrating the USB transceiver, Serial
Interface Engine (SIE), enhanced 8051 microcontroller, and a
programmable peripheral interface in a single chip, Cypress has
created a very cost effective solution that provides superior
time-to-market advantages.
The EZ-USB FX1 is more economical, because it incorporates
the USB transceiver and provides a smaller footprint solution
than the USB SIE or external transceiver implementations. With
EZ-USB FX1, the Cypress Smart SIE handles most of the USB
protocol in hardware, freeing the embedded microcontroller for
application specific functions and decreasing the development
time to ensure USB compatibility.
The General Programmable Interface (GPIF) and Master/Slave
Endpoint FIFO (8 or 16-bit data bus) provide an easy and
glueless interface to popular interfaces such as ATA, UTOPIA,
EPP, PCMCIA, and most DSP/processors.
Four Pb-free packages are defined for the family: 56 SSOP, 56
QFN, 100 TQFP, and 128 TQFP.
8051 Microprocessor
The 8051 microprocessor embedded in the FX1 family has 256
bytes of register RAM, an expanded interrupt system, three
timer/counters, and two USARTs.
8051 Clock Frequency
FX1 has an on-chip oscillator circuit that uses an external 24
MHz (±100 ppm) crystal with the following characteristics:
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Parallel resonant
Fundamental mode
500
μW
drive level
12 pF (5% tolerance) load capacitors.
An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz,
as required by the transceiver/PHY, and the internal counters
divide it down for use as the 8051 clock. The default 8051 clock
frequency is 12 MHz. The clock frequency of the 8051 is dynam-
ically changed by the 8051 through the CPUCS register.
The CLKOUT pin, which is three-stated and inverted using the
internal control bits, outputs the 50% duty cycle 8051 clock at the
selected 8051 clock frequency which is 48, 24, or 12 MHz.
USARTS
FX1 contains two standard 8051 USARTs, addressed by Special
Function Register (SFR) bits. The USART interface pins are
available on separate IO pins, and are not multiplexed with port
pins.
UART0 and UART1 can operate using an internal clock at 230
KBaud with no more than 1% baud rate error. 230 KBaud
operation is achieved by an internally derived clock source that
generates overflow pulses at the appropriate time. The internal
clock adjusts for the 8051 clock rate (48, 24, 12 MHz) such that
it always presents the correct frequency for 230-KBaud
operation.
Special Function Registers
Certain 8051 SFR addresses are populated to provide fast
access to critical FX1 functions. These SFR additions are shown
in
enhanced 8051 registers. The two SFR rows that end with ‘0’ and
‘8’ contain bit addressable registers. The four IO ports A–D use
the SFR addresses used in the standard 8051 for ports 0–3,
which are not implemented in the FX1. Because of the faster and
more efficient SFR addressing, the FX1 IO ports are not addres-
sable in the external RAM space (using the MOVX instruction).
Applications
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DSL modems
ATA interface
Memory card readers
Legacy conversion devices
Home PNA
Wireless LAN
MP3 players
Networking
The
section of the cypress website provides
additional tools for typical USB applications. Each reference
design comes complete with firmware source and object code,
schematics,
and
documentation.
Please
visit
for more information.
Functional Overview
USB Signaling Speed
FX1 operates at one of the three rates defined in the USB Speci-
fication Revision 2.0, dated April 27, 2000:
Full speed, with a signaling bit rate of 12 Mbps.
FX1 does not support the low speed signaling mode of 1.5 Mbps
or the high speed mode of 480 Mbps.
Figure 1. Crystal Configuration
C1
12 pF
24 MHz
C2
12 pF
12-pF capacitor values assumes
a trace capacitance of 3 pF per
side on a four layer FR4 PCA
20 × PLL
Note
1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a ‘1’ for UART0 and UART1, respectively.
Document #: 38-08039 Rev. *E
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