EM4069
EM4169
Timing Characteristics
VDD = 3.0 V, VSS = 0 V, fCOIL1 = 125 kHz square wave, VCOIL1 = 5V, TOP = 25°C, unless otherwise specified
Parameter
Symbol Condition
Min.
Typ.
Max.
Unit
Option : 64 RF periods per bit
Read bit period
EEPROM write time
Synchronization pattern phase 1
Synchronization pattern phase 2
Synchronization pattern phase 3
tRDB
tWee
tS1
tS2
tS3
64
RF periods
20
4.1
1.5
1.5
ms
ms
ms
ms
5.0
2.0
4.0
Option : 32 RF periods per bit
Read bit period
tRDB
tWee
tS1
32
RF periods
EEPROM write time
20
2.1
0.8
0.8
ms
ms
ms
ms
Synchronization pattern phase 1
Synchronization pattern phase 2
Synchronization pattern phase 3
2.5
1.0
2.0
tS2
tS3
RF periods represent periods of the carrier frequency emitted by the transceiver unit.
See figure 12 for Synchronization pattern phases.
Due to amplitude modulation of the coil-signal, the clock-extractor may miss clocks or add spurious clocks close to
the edges of the RF-envelope. This desynchronization will not be larger than 3 clocks per bit and must be taken into
account when developing reader software.
Block Diagram
Clock
Sequencer
Extractor
EEPROM
Data
Extractor
Control
Logic
Modulator
VDD
VSS
COIL1
CR
VSS
Power
Supply
ROM
Power on
Reset
Cbuf
Reset
Fig. 3
3
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EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
