PBA 313 01
PHD_OFF
Phase detector off control is active 'high'. Activate this signal
in transmit mode to open the phase locked loop (PLL)
employed in the VCO synthesizer section and enable modula-
tion of the carrier using the TX_DATA digital input. PHD_OFF
is activated after the initialization of the SYNT_ON signal and
the TX_ON signal, see figure 6 and table 2.
POR_EXT
External power on reset is active 'high'. An external power-
on-reset digital input signal that will reset the radio controller
and its registers. A reset will occur on the positive edge of
POR_EXT signal.
SYS_CLK_REQ
System clock request control is active 'high'. Once the crystal
oscillator bit (XOCTR, control register, bit #2) has been set,
use this control to switch off (sleep mode) and wake up
(idle and operating modes) the reference clock circuitry and
corresponding 13MHz and 1MHz clock output ports of the
module.
TX_CLK
1 MHz transmit clock digital output available for the baseband
circuitry when the POR_EXT and SYS_CLK_REQ (see above)
are both 'high'. TX_CLK changes value on rising edges of
SYS_CLK.
LPO_CLK
3.2 kHz low power oscillator clock digital output that is
adjustable by setting the internal LPOHI and LPOLO registers
(see Design Considerations). The clock output is available
as soon as the power supply is applied and POR_EXT is
'high' (figure 7). The LPO is necessary for wake-up timing
in the baseband circuitry, if the Ericsson baseband is used.
LPO_CLK must be trimmed to
1
/
2
LSB from 3.2 kHz or cali-
brated within 230 ppm, using SYS_CLK or TX_CLK.
Data Interface
Two digital signals are used for data flow over the air inter-
face.
TX_DATA
Transmit data digital control is active 'high'
12)
. The radio
module feeds Bluetooth data (1Mbit/s) directly to the radio
frequency modulator when PHD_OFF is activated. The total
delay from the TX_DATA pin to the ANT pin is typically
0.5µs.
RX_DATA
Receive data digital output is active 'high'. The radio module
latches out Bluetooth data (1 Mbit/s) on the RX_DATA pin on
each falling edge of SYS_CLK when RX_ON is activated. The
total delay from the ANT pin to the RX_DATA pin is typically
2.5µs.
Output Control
There are four digital output control signals available for con-
trolling external baseband circuitry.
POR
Power-on-reset digital output is activated after the power has
been applied to the Bluetooth radio or on a positive edge of
the POR_EXT digital input. POR has a transition from 'low'
to 'high' after four clock cycles have been delivered to the
baseband chip, see figure 7.
SYS_CLK
13 MHz system clock digital output available for the base-
band circuitry when the POR_EXT and SYS_CLK_REQ are
both 'high'. SYS_CLK will also be available during startup,
independent on the value of SYS_CLK_REQ, see figure 7.
12)
Data on the TX_DATA pin is digitally buffered before it is fed to the radio
frequency modulator. The polarity of this input can be set to normal by
writing ‘1’ or inverted by writing ‘0’ to bit 0 of the Enable register.
0
VCC
POR_EXT
SYS_CLK_REQ
0.5ms
1.0ms
1.5ms
2.0ms
Vcc
’1’
2.5ms
3.0ms
3.5ms
4.0ms
’0’ or ’1 ’
LPO_CLK
Control
Register
SYS_CLK
POR
10000XX
Figure 7. Powering up the module.
EN/LZT 146 65 R3B © Ericsson Microelectronics AB, October 2001
7
ERICSSON [ ERICSSON ]
