PBA 313 01
Register name
VCO/DAFC/Delay
Channel
RSSI
XO-trim
ID
LPO-hi
LPO-lo
Control
Modulation
Current
Enable
# bits
8
8
5
6
8
1
8
7
8
3
8
R or W
W
W
R
W
R
W
W
W
W
W
W
Address
010001
2
= 17
10
010010
2
= 18
10
010011
2
= 19
10
010101
2
= 20
10
010100
2
= 21
10
010110
2
= 22
10
010111
2
= 23
10
011000
2
= 24
10
011001
2
= 25
10
Value at reset
00000X00
00000010
XXXUUUUU
XX 0 0 0 0 0 0
0 0 0 1 VVVV
XXXXXXX 0
00000000
X 1 0 0 0 0 XX
00000000
0 0 0 XXXXX
UUUUUUUU
Recommended value
1111 1011
2
= 251
10
Bit two set to 1 to enable SYS_CLK_REQ
0100 0000
2
= 64
10
0000 0000
2
= 0
10
1011 1111
2
= 191
10
W = Writable, R = Readable, X = Not applicable, U = Undefined, V = Version number
Table 5. Data registers in the radio controller.
1
SI_CLK
SI_CMS
5
10
15
20
5
SI_CDI
I0
i0
I1
i1
I2
i2
I3
i3
I4
i4
I5
i5
D0
D1
D2
D3
D4
D5
D6
D7
SI_CDO
Q0 Q1 Q2 Q3
Q4 Q5
Q6 Q7
Capture DR
Run
Control/Idle
Select
DR-Scan
Select
DR-Scan
Shift DR
Select
IR-Scan
Figure 10. Reading and updating a data register. A data register is selected by entering the Shift IR state using SI_CMS, and
transferring the appropriate bit code to the instruction register using SI_CDI (I[5:0]=01YYYY, where YYYY is the address of the
register). Moving to the Shift-DR state, eight bits of register data can then be transferred on SI_CDI and SI_CDO. The data register
selected by the instruction register is updated when the SI controller enters the Update-DR state. At the end of the data register
access, the SI controller is once again held in the Run Control/Idle state.
Serial interface example
Writing the value 77 to the Channel register selects Bluetooth
channel 75 (i.e. 2477 MHz) for transmission. This will simulta-
neously read the RSSI measurement for the latest received
packet header. The normal operation sequence is:
• Point out the Channel register, this is done by performing
an IR-scan. The SI_CMS signal should be controlled as
shown in figure 10. When in the Shift-IR state the value
010010 should be shifted in on the SI_CDI input (LSB first).
When in the Run Control/Idle state the Instruction Register
is updated.
• Write the new channel value, this is done by performing
a DR-scan. The SI_CMS signal should be controlled as
shown in figure 10. When in the Shift-DR state, SI_CDI=
01001101 should be shifted in (LSB first). When in the Run
Control/Idle state the Channel register is updated.
If no other register has been addressed then the Channel
register contents are still in the IR, therefore only a new
DR-scan needs to be done to change to another frequency
channel.
Design Considerations
Power-up sequence
The start-up sequence is as follows, see figure 11 for typical
timing:
1. The start-up sequence starts with a Power-On-Reset
(POR_EXT) or by applying power to VCC. This resets all the
registers in the radio controller.
2. The LPO_CLK starts to oscillate.
EN/LZT 146 65 R3B © Ericsson Microelectronics AB, October 2001
Exit DR
Shift IR
JTAG
controller
state
Run
Control/Idle
Update DR
Capture IR
Update IR
Exit IR
9
ERICSSON [ ERICSSON ]
