PBD 3517/1
Functional Description
The circuit, PBD 3517/1, is a high
perform-ance motor driver, intended to
drive a stepper motor in a unipolar, bilevel
way. Bilevel means that during the first
time after a phase shift, the voltage
across the motor is increased to a second
voltage supply, V
SS
, in order to obtain a
more-rapid rise of current, see figure 11.
The current starts to rise toward a
value which is many times greater than
the rated winding current. This compen-
sates for the loss in drive current and loss
of torque due to the back emf of the
motor.
After a short time, t
On
, set by the
monostable, the bilevel output is switched
off and the winding current flows from the
V
MM
supply, which is chosen for rated
winding current. How long this time must
be to give any increase in performance is
determined by V
SS
voltage and motor
data, the L/R time-constant.
In a low-voltage system, where high
motor performance is needed, it is also
possible to double the motor voltage by
adding a few external components, see
figure 14.
The time the circuit applies the higher
voltage to the motor is controlled by a
monostable flip-flop and determined by
the timing components R
T
and C
T
.
The circuit can also drive a motor in
traditional unipolar way.
An inhibit input (INH) is used to switch
off the current completely.
STEP — Stepping pulse
One step is generated for each negative
edge of the STEP signal. In half-step
mode, two pulses will be required to move
one full step. Notice the set up time, t
s
, of
DIR and HSM signals. These signals
must be latched during the negative edge
of STEP, see timing diagram, figure 3.
DIR — Direction
DIR determines in which direction steps
will be taken. Actual direction depends on
motor and motor connections. DIR can be
changed at any time, but not simultan-
eously with STEP, see timing diagram,
figure 3.
HSM determines whether the motor will
be controlled in full-step or half-step
mode. When pulled low, a step-pulse will
correspond to a half step of the motor.
HSM can be changed at any time, but not
simultaneously with STEP, see timing
diagram, figure 3.
Logic inputs
All inputs are LS-TTL compatible. If any
of the logic inputs are left open, the
circuit will accept it as a HIGH level. PBD
3517/1 contains all phase logic
necessary to control the motor in a
proper way.
V
SS
V
MM
+ 5V
+
+
+
D3
PBD 3517/1
C
5
V
SS
15
C
3
V
CC
C
4
D2
D1
V
CC
16
R11
PQR
RC
12
R10
CMOS, TTL-LS
Input / Output-Device
Mono
F-F
13
L
A
R9
STEP
CW / CCW
HALF / FULL STEP
NORMAL /INHIBIT
(Optional Sensor)
R8
R
T
C
T
STEP
DIR
HSM
INH
O
A
O
B
7
6
10
11
9
8
14
L
B
MOTOR
Phase
Logic
P
A
1
P
B2
P
B1
P
A2
P
A1
D3-D6
2
5
4
P
B
3
GND
GND
D3-D6 are
UF 4001 or
BYV 27
trr < 100 ns
GND (V
MM
,V
SS
)
GND (V
CC
)
Figure 14.
Typical
application.
V
MM
+ 5V
+
+
R1
C
4
V
SS
15
PBD 3517/1
C
3
V
CC
D1
V
CC
16
R10
PQR
Q1
RC
12
CMOS, TTL-LS
Input / Output-Device
Mono
F-F
13
L
A
C1
+
R9
STEP
CW / CCW
HALF / FULL STEP
NORMAL /INHIBIT
(Optional Sensor)
R8
R
T
C
T
STEP
DIR
HSM
INH
O
A
O
B
7
6
10
11
9
8
14
L
B
Q3
R2
Phase
Logic
P
A
1
P
B2
P
B1
P
A2
P
A1
Equal to
Phase A
R4
1/2 MOTOR
R12
Q5
Q6
R13
P
B
2
5
4
R5
3
GND
GND
GND (V
CC
)
GND (V
MM
,V
SS
)
Figure 15. Voltage
doubling with
external
transistors.
6
ERICSSON [ ERICSSON ]
