PBD 3517/1
Phase outputs use a current-sinking
method to drive the windings in a unipolar
way. A common resistor in the center tap
will limit the maximum motor current.
Fast free-wheeling diodes must be
used to protect output transistors from
inductive spikes. Alternative solutions are
shown in figures 21 through 25 on pages
6 - 10.
Series diodes in V
MM
supply, prevent
V
SS
voltage from shorting through the V
MM
power supply. However, these may be
omitted if no bilevel is used. The V
SS
pin
must not be connected to a lower voltage
than V
MM
, but can be left unconnected.
Zero outputs
Ø
A
and Ø
B
, “zero A” and “zero B,” are
open-collector outputs, which go high
when the corresponding phase output is
inhibited by the half-step-mode circuitry. A
pull-up resistor should be used and
connected to a suitable supply voltage (5
kohms for 5V logic). See “Bipolar phase
logic output.”
Interference
To avoid interference problems, a good
idea is to route separate ground leads to
each power supply, where the only
common point is at the 3517/1’s GND pin.
Decoupling of V
SS
and V
MM
will improve
performance. A 5 kohm pull-up resistor at
logic inputs will improve level definitions,
especially when driven by open-collector
outputs.
OB
LB
PB1
PB2
PA1
PA2
LA
OA
L
P
P
P
P
P
P
L
DIR
INH
HSM
STEP
OB
LB
PB1
PB2
PA1
PA2
LA
OA
H
L
H
P
L
P
P
P
P
P
P
L
Figure 16. Full-step mode, forward. 4-step sequence. Gray-code +90° phase shift.
DIR
INH
HSM
STEP
H
L
H
P
Figure 17. Full-step mode, reverse. 4-step sequence. Gray-code -90° phase shift.
DIR
INH
HSM
STEP
OB
LB
PB1
PB2
PA1
PA2
LA
OA
H
L
L
P
C
P
P
P
P
P
P
P
P
Figure 18. Half-step mode, forward. 8-step sequence.
DIR
INH
HSM
STEP
OB
LB
PB1
PB2
PA1
PA2
LA
OA
L
L
L
P
C
Input and Output Signals for
Different Drive Modes
The pulse diagrams, figures 16 through
20, show the necessary input signals and
the resulting output signals for each drive
mode.
On the left side are the input and output
signals, the next column shows the state
of each signal at the cursor position
marked “C.”
STEP is shown with a 50% duty cycle,
but can, of course, be with any duty cycle,
as long as pulse time (t
p
) is within
specifications.
P
A
and P
B
are displayed with low level,
showing current sinking.
L
A
and L
B
are displayed with high level,
showing current sourcing.
P
P
P
P
P
P
P
P
Figure 19. Half-step mode, reverse. 8-step sequence.
DIR
INH
HSM
STEP
OB
LB
PB1
PB2
PA1
PA2
LA
OA
L
H
L
P
C
P
P
H
H
H
H
P
P
Figure 20. Half-step mode, inhibit.
8
ERICSSON [ ERICSSON ]
