PBL 402 15
The 3-Wire Control Bus Interface.
The 3-wire serial bus interface controls the various IC parameters and consists of 3 lines, strobe, data and clock ( ST, D, CK ).
Alternatively, selected power control modes may be controlled by 3 hard-wire control lines ( EN, RXEN, TXEN ).
The 3-wire bus is active when either EN or ST, or both are active. The strobe signal is used to enable the clock and latch the
data frame. Each frame consists of 24 bits, built from a word field and a data field. The word address is the last bit to be sent
( LSB ), with the data field being the proceeding 23 bits. Data on D is shifted into the frame register by clock CK.
The 3-wire interface allows setting of word A and word B. These control the IC configuration.
Frame definition:
MSB
First in
Data
Frame:
Description
tag:
LSB
Last in
Word
Address
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
W0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
Digital Interface:
Pin
ST
CK
D
EN
RXEN
TXEN
Spec.
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Description
The control section is powered up when ST is low. Data is latched on the rising edge.
ST has an internal 160kΩ pull up resistor to V
CC
PLL.
3-wire interface clock. May be running continuously, but to minimise the risk of VCO spurious it is
recommended that the clock only runs when required.
3-wire interface data. Data latched by rising edge of CK.
IC enable control. Active low. The control section is powered when EN is active.
EN has an internal 160 kΩ pull up resistor to V
CC
PLL.
Receiver enable. Active low.
Transmitter enable. Active low.
Digital Interface:
Parameter
Serial clock frequency
Delay strobe to first rising clock
Data setup time: D to CK
Data hold time
Clock pulse widh high
Strobe hold time high
Condition
Symbol
f
CK
t
SCK
t
DS
t
DH
t
CKW
t
SW
Min.
288
18
18
18
144
Typ.
Max.
13.9
Unit
MHz
ns
ns
ns
ns
ns
9
ERICSSON [ ERICSSON ]
