CLC1003
2
Overdrive Recovery
An overdrive condition is defined as the point when either
one of the inputs or the output exceed their specified
voltage range. Overdrive recovery is the time needed for the
amplifier to return to its normal or linear operating point. The
recovery time varies based on whether the input or output
is overdriven and by how much the ranges are exceeded.
The CLC1003 will typically recover in less than 20ns from
an overdrive condition. Figure 5 shows the CLC1003 in an
overdriven condition.
3
2
V
IN
= .8V
pp
G=5
2
1
Maximum Power Dissipation (W)
1.5
SOIC-8
1
0.5
TSOT-6
0
-40
-20
0
20
40
60
80
100
120
Ambient Temperature (°C)
2
1
0
Output
-1
-2
-3
0
0.25
0.5
0.75
1
1.25
1.5
Input Voltage (V)
Figure 3. Maximum Power Derating
Driving Capacitive Loads
Increased phase delay at the output due to capacitive loading
can cause ringing, peaking in the frequency response, and
possible unstable behavior. Use a series resistance, R
S
,
between the amplifier and the load to help improve stability
and settling performance. Refer to Figure 4.
Input
Output Voltage (V)
Input
1
0
-1
-1
-2
-2
1.75
2
Time (us)
+
-
R
f
R
g
R
s
C
L
R
L
Figure 5: Overdrive Recovery
Output
Considerations for Offset and Noise Performance
Offset Analysis
There are three sources of offset contribution to consider;
input bias current, input bias current mismatch, and input
offset voltage. The input bias currents are assumed to be
equal with and additional offset current in one of the inputs
to account for mismatch. The bias currents will not affect
the offset as long as the parallel combination of R
f
and R
g
matches R
t
. Refer to Figure 6.
R
g
R
f
+V
s
Figure 4. Addition of R
S
for Driving Capacitive Loads
The CLC1003 is capable of driving up to 300pF directly, with
no series resistance. Directly driving 500pF causes over
4dB of frequency peaking, as shown in the plot on page 6.
Table 1 provides the recommended R
S
for various capacitive
loads. The recommended R
S
values result in ≤ 1dB peaking
in the frequency response. The Frequency Response vs.
C
L
plots, on page 6, illustrate the response of the CLC1003.
C
L
(pF)
500
1000
3000
–
R
t
CLC1003
+
R
L
R
S
(Ω)
10
7.5
4
-3dB BW (MHz)
27
20
15
IN
-V
s
Figure 6: Circuit for Evaluating Offset
The first place to start is to determine the source resistance.
If it is very small an additional resistance may need to be
added to keep the values of R
f
and R
g
to practical levels.
For this analysis we assume that R
t
is the total resistance
present on the non-inverting input. This gives us one
equation that we must solve:
Rev 1D
Table 1: Recommended R
S
vs. C
L
For a given load capacitance, adjust R
S
to optimize the
tradeoff between settling time and bandwidth. In general,
reducing R
S
will increase bandwidth at the expense of
additional overshoot and ringing.
© 2007-2014 Exar Corporation
13 / 17
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