CLC1003
R
t
= R
g
||R
f
This equation can be rearranged to solve for R
g
:
R
g
= (R
t
* R
f
) / (R
f
- R
t
)
The other consideration is desired gain (G) which is:
G = (1 + R
f
/R
g
)
By plugging in the value for R
g
we get
R
f
= G * R
t
And R
g
can be written in terms of R
t
and G as follows:
R
g
= (G * R
t
) / (G - 1)
The complete input offset equation is now only dependent
on the voltage offset and input offset terms given by:
VI
OS
=
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. Exar has evaluation boards to
use as a guide for high frequency layout and as an aid in
device testing and characterization. Follow the steps below
as a basis for high frequency layout:
■■
The complete equation can be simplified to:
2
v
o
=
3
∗
4kT
∗
G
∗
RT
+
e
n
G
(
) ( )
2
+
2
∗
i
n
∗
RT
(
)
2
It’s easy to see that the effect of amplifier voltage noise
is proportionate to gain and will tend to dominate at large
gains. The other terms will have their greatest impact at
large R
t
values at lower gains.
(
V
IO
)
+
(
I
OS
∗
RT
)
( ) (
V
IO
2
2
2
Include 6.8µF and 0.1µF ceramic capacitors for power supply
decoupling
Place the 6.8µF capacitor within 0.75 inches of the power pin
Place the 0.1µF capacitor within 0.1 inches of the power pin
Remove the ground plane under and around the part,
especially near the input and output pins to reduce parasitic
capacitance
Minimize all trace lengths to reduce series inductances
And the output offset is:
VO
OS
=
G
∗
+
I
OS
∗
RT
■■
■■
)
2
■■
■■
Noise analysis
The complete equivalent noise circuit is shown in Figure 7.
R
g
+–
Refer to the evaluation board layouts below for more
information.
Evaluation Board Information
+–
R
f
–
R
g
+–
+
–
+–
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board #
CEB002
CEB003
CLC1003
+
R
L
Products
CLC1003 in TSOT
CLC1003 in SOIC
Figure 7: Complete Equivalent Noise Circuit
The complete noise equation is given by:
2
v
o
2
RF
=
vorext
+
e
n
1
+
RG
2
Where V
orext
is the noise due to the external resistors and
is given by:
2
v
o
=
e
n
1
+
© 2007-2014 Exar Corporation
w
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in
Figures 8-12 These evaluation boards are built for dual-
supply operation. Follow these steps to use the board in a
single-supply application:
1. Short -V
S
to ground.
2. Use C3 and C4, if the -V
S
pin of the amplifier is not
directly connected to the ground plane.
+
i
bp
∗
RT 1
+
RF
RG
2
+
i
bn
∗
RF
(
)
2
RF
RG
2
+
e
G
∗
RF
RG
2
+
e
F
2
14 / 17
Rev 1D
EXAR [ EXAR CORPORATION ]
