MP8830
ADC Gain and Offset Control
Each channel of the MP8830 contains a 10-bit ADC, a 10-bit
DAC with MSB = 1 (9 active bits) driving the positive reference,
and a 6-bit DAC driving the negative reference of the ADCs lad-
der network.
The relationship between the ADC gain and offset and the
DAC data can be expressed mathematically.
Assign the terms V
RT
and V
RB
to represent the voltages for
the ADC full scale and black levels. DgainA and DoffsetA repre-
sent the digital value for the gain and offset parameters set by
the DACs for channel A.
V
RT
and V
RB
are defined by the equation:
DgainA
+
(1
)
)
<
1.3
<
V
REF
)
V
RB
2
9
DoffsetA
)
<
0.16
<
V
REF
2
6
DgainA
)
<
1.3
<
V
REF
2
9
V
CAL
10 pF
V
SS
V
REF
range for each channel can be either the same or different
depending on the application and nominal channel gain re-
quired. A higher V
REF
provides lower channel gain.
AV
DD
Sample
VINMX
250Ω
100Ω
A
IN
8 pF
V
SS
AV
DD
VINMX
Sample
+
VRT + VRB
2
–
1.5 pF
Sample
25 pF
100Ω
V
RT
V
RB
+
(1
)
Figure 8. ADC Input Equivalent Circuit
V
RT
*
V
RB
+
(1
)
ADC Analog Input
This part has a switched capacitor type input circuit. This
means that the input impedance changes with the phase of the
input clock.
Figure 8.
shows an equivalent input circuit.
AV
DD
V
REF
AFORC
LM324A
ASENS
500Ω
Channel
A
↓
IREF
Circuitry
+
–
VCAL and VINMX
VCAL voltage is connected through an analog mux to all 3
channel inputs at VINMX=1. VCAL can then be used to normal-
ize all three ADC input voltage to output states. It can be used for
testing as well as building calibration tables for all three chan-
nels.
↓
6.75 IREF
Internal
V
Common
Bonding
Wire & pin
Internal Pad
~0.7Ω
AGND2 Pin
Supply and Grounds
AGND1, BGND1, CGND1, and GND3 should be connected
under the package to make their common impedance as low as
possible. AGND2, BGND2, CGND2 should also be connected
to this ground.
Use a single supply to drive all of the V
DD
pins. AV
DD
, BV
DD
,
CV
DD
, V
DD3
should be connected to a common supply plane
which forms a supply / ground plane with the analog ground
plane. In addition, local decoupling (preferably 0.1 uFchip type)
should be connected between each analog V
DD
pin and its clos-
est analog ground.
A decoupling capacitor (preferably 0.1 uFchip type) should
be connected across pin 1 and 64 and between pin 44 and 43. A
DV
DD
to DGND supply/ground plane should also be provided.
Figure 7. Driving the AFORC and ASENS Pins
(Channel A Example)
Channel Bias Circuitry
The gain DAC and the offset DAC for each channel have a
combined bias generator for setting their full scale range. An ex-
ternal op amp is required and is connected per
Figure 7.
The
Rev. 1.00
12
EXAR [ EXAR CORPORATION ]
