MP8830
ELECTRICAL CHARACTERISTICS
Unless otherwise specified: AV
DD
= DV
DD
= 5 V, DGND = AGND = 0 V, V
REF
= AV
DD
0.2
Temperature = 0 to 60°C
1
A/D Converters
Parameter
Resolution
Differential Non-Linearity
Differential Non-Linearity
Integral Non-Linearity
Integral Non-Linearity
Zero Scale Error
Symbol
N
DNL
DNL
INL
INL
ZSE
–15
Min
10
–1
–1
0.75
0.5
2
1.5
2
2
2.75
2
9
Typ
Max
Units
Bits
LSB
LSB
LSB
LSB
mV
Gain DAC = 000 (hex), offset DAC = 00 (hex).
Monotonicity guaranteed.
Gain DAC = 1FF (hex), offset DAC = 00 (hex).
Monotonicity guaranteed.
Gain DAC = 000 (hex), offset DAC = 00 (hex),
Best fit straight line.
Gain DAC = 1FF (hex), offset DAC = 00 (hex),
Best fit straight line.
Measured with offset and gain DACs set to
000. Offset is defined as the difference be-
tween the clamp voltage and the analog input
voltage which results in the transition of the
ADC code from 004 to 005.
Measured as the change in the ZSE over tem-
perature. This error does not include the error
introduced by the external V
REF
amplifier or
external V
REF
resistor divider.
The digitizing range is set with the Gain DAC
and offset DAC. Please note A
IN
(min) is
VCLP – 4 LSB = V
RB
and A
IN
(max) is GFS
(max) + ZSR (max) + VCLP – 4 LSB.
The conversion rate is determined by the tim-
ing diagram and timing specifications. Set by
the CVL period.
Assuming A
IN
voltage remains within the spe-
cified digitizing range based on the offset and
gain DAC codes.
Measured with A
IN
DC = 2.5 V and AENL =
low.
Test Conditions/Comments
Zero Scale Drift
2
ZSD
50
µV/°C
DC Input Range
A
IN
VCLP
–5mV
2.92 V +
VCLP
–5 mV
V
Data Rate
FS
1.25
MSPS
Analog Input Voltage Change from
Sample to Sample
2
Input Capacitance
2
DA
IN
0
FS
V
C
IN
45
pF
Gain DAC
Resolution
Differential Non-Linearity
Integral Non-Linearity
Gain DAC Full Scale
(V
RT
– V
RB
)
Gain DAC Zero Scale
(V
RT
– V
RB
)
Maximum Gain Change per Cycle
2
N
DNL
INL
GFS
2.6
2.68
–1
9
+2.25
+2
2.76
Bits
LSB
LSB
V
Gain DAC = 1FF
V
RT
is the top of the ADC reference ladder.
Refer to block diagram.
Gain DAC = 000
V
RB
is the bottom of the ADC reference lad-
der. Refer to block diagram.
After the specified maximum change in gain
DAC setting, the ADC should output the same
code
1
LSB for all of the following conver-
sions assuming the analog input remains
fixed, i.e. DC.
GZS
1.22
1.26
1.3
V
MGC
50
% FSR
Settling Time (MGC)
2
ts-gd
200
ns
Rev. 1.00
4
EXAR [ EXAR CORPORATION ]
