FAN5026 — Dual DDR / Dual-Output PWM Controller
Electrical Characteristics
Recommended operating conditions, unless otherwise noted.
Symbol
Power Supplies
I
VCC
I
SINK
I
SOURCE
I
SD
V
UVLO
V
UVLOH
Oscillator
f
osc
V
PP
V
RAMP
G
Parameter
Conditions
LDRV, HDRV Open, V
SEN
Forced
Above Regulation Point
Shutdown (EN-0)
V
IN
= 15V
V
IN
= 0V
Rising V
CC
Falling
Min.
Typ.
Max.
Units
V
CC
Current
V
IN
Current, Sinking
V
IN
Current, Sourcing
V
IN
Current, Shutdown
UVLO Threshold
UVLO Hysteresis
Frequency
Ramp Amplitude
Ramp Offset
Ramp / V
IN
Gain
2.2
3.0
30
A
A
A
A
A
V
V
mV
10
-15
4.30
4.10
4.55
4.25
300
255
300
2
1.25
0.5
125
250
0.891
0.900
5
1.5
30
-30
1
4.75
4.45
345
KHz
V
V
V
mV/V
mV/V
V
IN
= 16V
V
IN
= 5V
V
IN
≤
3V
1V < V
IN
< 3V
Reference and Soft-Start
V
REF
I
SS
V
SS
Internal Reference Voltage
Soft-Start Current
Soft-Start Complete Threshold
Load Regulation
I
SEN
UVLO
I
SNS
V
SEN
Bias Current
% of Set Point, 2 s Noise Filter
% of Set Point, 2 s Noise Filter
R
ILIM
= 68.5KΩ, Figure 12
Over-Voltage Threshold
Over-Current Threshold
Minimum Duty Cycle
Output Drivers
HDRV Output Resistance
LDRV Output Resistance
Power-Good Output and Control Pins
Lower Threshold
Upper Threshold
PG Output Low
Leakage Current
PG2/REF2OUT Voltage
DDR, EN Inputs
V
INH
V
INL
Input High
Input Low
2
0.8
V
V
% of Set Point, 2 s Noise Filter
% of Set Point, 2 s Noise Filter
IPG = 4mA
V
PULLUP
= 5V
DDR = 1, 0 mA < I
REF2OUT
≤10mA
99.00
-86
108
-94
116
0.5
1
1.01
%
%
V
A
%
V
REF2
Sourcing
Sinking
Sourcing
Sinking
12
2.4
12
1.2
15
4.0
15
2.0
Ω
Ω
UVLO
TSD
Under-Voltage Shutdown
I
OUTX
from 0 to 5A, V
IN
from 5 to 15V
-2
50
70
115
112
10
80
75
120
140
At Startup
0.909
V
A
V
+2
120
80
125
168
%
nA
%
%
A
%
PWM Converters
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
www.fairchildsemi.com
6
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
