FAN5026 — Dual DDR / Dual-Output PWM Controller
Initialization and Soft Start
Assuming EN is HIGH, FAN5026 is initialized when V
CC
exceeds the rising UVLO threshold. Should V
CC
drop
below the UVLO threshold, an internal power-on reset
function disables the chip.
The voltage at the positive input of the error amplifier is
limited by the voltage at the SS pin, which is charged
with a 5µA current source. Once C
SS
has charged to
V
REF
(0.9V) the output voltage is in regulation. The time
it takes SS to reach 0.9V is:
Since
=
∙
100 +
(
)
(3b)
and at the ILIM 0.9V threshold:
= 12 ∙
therefore:
0.9
=
10.8
(3c)
0.9 xC
SS
t
0.9
=
5
where t
0.9
is in seconds if C
SS
is in F.
(1)
=
10.8 100 +
∙
(
)
(3d)
When SS reaches 1.5V, the power-good outputs are
enabled and Hysteretic Mode is allowed. The converter
is forced into PWM Mode during soft-start.
Current Processing Section
The following discussion refers to Figure 12.
The current through the R
SENSE
resistor (I
SNS
) is
sampled (typically 400ns) after Q2 is turned on, as
shown in Figure 12. That current is held and summed
with the output of the error amplifier. This effectively
creates a current-mode control loop. The resistor
connected to ISNSx pin (R
SENSE
) sets the gain in the
current feedback loop. For stable operation, the voltage
induced by the current feedback at the PWM
comparator input should be set to 30% of the ramp
amplitude at maximum load current and line voltage.
The following expression estimates the recommended
value of R
SENSE
as a function of the maximum load
current (I
LOAD(MAX)
) and the value of the MOSFET
R
DS(ON)
:
Current limit (I
LIMIT
) should be set high enough to allow
inductor current to rise in response to an output load
transient. Typically, a factor of 1.2 is sufficient. In
addition, since I
LIMIT
is a peak current cut-off value,
multiply I
LOAD(MAX)
by the inductor ripple current (e.g.
25%). For example, in Figure 6, the target for I
LIMIT
:
I
LIMIT
> 1.2 x 1.25 x 1.6 x 2A
≈
5A
(4)
=
10.8 100 +
∙
(
)
=
∙
(
30% ∙ 0.125 ∙
(
)
)
(
∙ 4.1
)
− 100
(2a)
R
SENSE
must, however, be kept higher than:
Since the tolerance on the current limit is largely
dependent on the ratio of the external resistors, it is
fairly accurate if the voltage drop on the switching-node
side of R
SENSE
is an accurate representation of the load
current. When using the MOSFET as the sensing
element, the variation of R
DS(ON)
causes proportional
variation in the I
SNS
. This value varies from device to
device and has a typical junction temperature
coefficient of about 0.4%/°C (consult the MOSFET
datasheet for actual values), so the actual current limit
set point decreases proportional to increasing MOSFET
die temperature. A factor of 1.6 in the current limit set
point should compensate for MOSFET R
DS(ON)
variations, assuming the MOSFET heat sinking keeps
its operating die temperature below 125°C.
Q2
LDRV
ISNS
R
SENSE
=
(
)
∙
(
)
150
µ
− 100
(2b)
The 100 is the internal resistor in series with the
ISNSx pins and has ±15% typical variation. Because
R
SENSE
is in series with the internal 100 resistor, the
gain in the current feedback loop and the current limit
accuracy is affected if R
SENSE
is close to 100 .
R1
PGND
Setting the Current Limit
A ratio of I
SNS
is compared to the current established
when a 0.9V internal reference drives the ILIM pin. The
threshold is determined as follows:
Figure 11.
Improving Current-Sensing Accuracy
9
=
4
3
= 12 ∙
(3a)
More accurate sensing can be achieved by using a
resistor (R1) instead of the R
DS(ON)
of the FET, as shown
in Figure 11. This approach causes higher losses, but
yields greater accuracy in both V
DROOP
and I
LIMIT
. R1 is a
low value resistor (e.g. 10mΩ).
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© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
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