FDP8896
Test Circuits and Waveforms
V
DS
BV
DSS
L
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
DUT
t
P
0V
R
G
-
I
AS
V
DD
V
DD
t
P
V
DS
+
I
AS
0.01Ω
0
t
AV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
V
DS
V
DD
L
V
GS
V
DS
Q
g(5)
V
DD
-
DUT
I
g(REF)
V
GS
= 1V
0
Q
g(TH)
Q
gs
I
g(REF)
0
Q
gd
Q
gs2
V
GS
= 5V
Q
g(TOT)
V
GS
V
GS
= 10V
+
Figure 17. Gate Charge Test Circuit
Figure 18.
Gate Charge Waveforms
V
DS
t
ON
t
d(ON)
R
L
V
DS
90%
t
r
t
OFF
t
d(OFF)
t
f
90%
V
GS
+
V
DD
-
DUT
0
10%
10%
R
GS
V
GS
V
GS
0
10%
50%
PULSE WIDTH
90%
50%
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
©2004 Fairchild Semiconductor Corporation
FDP8896 Rev. A1