FMP1617CCx
CMOS LPRAM
LOW POWER MODES
1. Mode Register Set
A19 ~ A5
A4
A3
A2
A1
A0
Array On/Off
on /ZZ
ZZ
0
Half Selection
Array Refresh Area
Enable/Disable
/ZZ Enable/Disable
A4
Array On/Off on /ZZ
A3
Type
Type
0
1
Deep Power Down Enable
DPD Disable (Default)
0
1
Partial Array Refresh Mode (Default)
Reduced Memory Size Mode
Note: If the register is written to enable the Deep
Power Down, the part will go into Deep Power Down
during the following time that /ZZ is driven low and
there is no MRS update. When /ZZ is driven high, all
of the register settings will return to default state for
the part (i.e. full array refresh, Deep Power Down
Disabled).
Note: The RMS(Reduced Memory Size) mode is enabled after
/ZZ goes high and remains enabled after /ZZ goes high. To
change to a different mode, the mode register will have to be
rewritten.
Half Selection (Top / Bottom)
Array Refresh Area
A2
0
Type
Bottom (Default)
Top
A1
0
A0
0
Type
Full Array (Default)
RFU
1
0
1
1
0
½ Array
1
1
¼ Array
2. MRS Update
tWC
Address
tWR(4)
tAS(3)
tCW(2)
/CS
tAW
tBW
/UB, /LB
tWP(1)
/WE
/ZZ
tZZWE
Register Write Start
Register Write
Complete
Register Update
Complete
The register update take place on the rising edge of /ZZ. Once the register is updated, the next time /ZZ goes low, without any
updates to the register starting within the tZZWE max time of 1us, the part will refresh the array selected. The data bus is a
don’t care When /ZZ is low during the register updates.
Revision 0.1
Jun. 2006
10
FIDELIX [ FIDELIX ]
