FMP1617CC0(7)
CMOS LPRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
1TTL
Input pulse level : 0.2 to VCC-0.2V
30pf
Input rising and falling time : 5ns
Input and output reference voltage : 0.5*VCCQ
Output load(see right) : CL=30pF+1TTL
AC CHARACTERISTICS(VCC=1.7V~1.95V)
Speed Bins
Parameter List
Symbol
70ns
85ns
Units
Min
70
-
Max
20k
70
70
25
70
-
Min
85
-
Max
20k
85
85
30
85
-
Read Cycle Time
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
Output Enable to Valid Output
tCO
tOE
tBA
-
-
-
-
/UB, /LB Access Time
-
-
Chip Select to Low-Z Output
/UB, /LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High- Z Output
/UB, /LB Disable to High- Z Output
Output Disable to High- Z Output
Output Hold from Address Change
tLZ
10
10
5
10
10
5
Read
tBLZ
tOLZ
tHZ
-
-
-
-
0
5
0
5
tBHZ
tOHZ
tOH
0
5
0
5
0
5
0
5
5
-
5
-
Write Cycle Time
tWC
70
20k
85
20k
ns
Chip Select to End of Write
Address Set-up Time
tCW
tAS
60
0
-
70
0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
Address Valid to End of Write
/UB, /LB Valid to End of Write
Write Pulse Width
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
60
60
50
0
-
70
70
60
0
-
-
-
Write
-
-
Write Recovery Time
-
-
Write to Output High-Z
Data to Write Time Overlap
0
5
0
5
20
0
-
20
0
-
Data Hold from Write Time
End Write to Output Low-Z
-
-
-
-
tOW
tPC
5
5
Page Mode Cycle Time
Page Mode Address Access Time
Maximum Cycle Time
25
-
-
30
-
-
Page
tPAA
tMRC
tCP
25
20k
-
30
20k
-
-
-
/CS High Pulse Width
10
10
1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High.
Revision 0.1
Jun. 2006
5
FIDELIX [ FIDELIX ]
