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FMP1617CC7-HXXX 参数 Datasheet PDF下载

FMP1617CC7-HXXX图片预览
型号: FMP1617CC7-HXXX
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×16位超低功耗和低电压全CMOS RAM [1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM]
分类和应用:
文件页数/大小: 10 页 / 208 K
品牌: FIDELIX [ FIDELIX ]
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FMP1617CC0(7)
WRITE CYCLE (4)
Address
tCW(2)
tWR(4)
CMOS LPRAM
tWC
(/UB, /LB controlled)
/CS1
CS2
tAW
/UB, /LB
tAS(3)
tBW
tWP(1)
/WE
Data in
Data Out
tDW
tDH
Data Valid
High-Z
High-Z
1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with
asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write
ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to
the end of write.
2. tCW is measured from the /CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.
PAGE WRITE CYCLE
(Address controlled, CS2=V
IH
)
tMRC
tWC
tPC
tPC
tPC
tPC
tPC
tPC
tPC
A0~A3
A4~A20
/CS1
CS2
/UB, /LB
tAS(3)
/WE
tDW
tDH
tDW
tDH
tDW
tDH
tDW
tDH
tDW
tDH
tDW
tDH
tDW
tDH
tDW
tDH
Data in
High-Z
tWHZ
Data Valid
Data Valid
Data Valid
Data Valid
Data Valid
Data Valid
Data Valid
Data Valid
High-Z
tOW
Data Out
Data Undefined
1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with
asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write
ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to
the end of write.
2. tCW is measured from the /CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.
6. In case page address is over 3ns, write to the invalid address can occur.
9
Revision 0.1
Jun. 2006