ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
CS
0.2 V
DD
t
LEAD
t
LAG
SCLK
0.7 V
DD
0.2 V
DD
t
SI(SU)
t
SI(HOLD)
SI
0.7 V
DD
0.2 V
DD
MSB IN
t
SO(EN)
t
VALID
0.7 V
DD
0.2 V
DD
t
SO(DIS)
SO
MSB OUT
LSB OUT
Figure 4. SPI Timing Characteristics
VPWR
VDD
WAKE
INT
CS
Wake-Up From
Closed Switch
Power-Up
Normal Mode
Tri-State
Command
(Disable
Tri-State)
Sleep
Command
Sleep Mode
Normal
Mode
Sleep Command
Sleep Mode
Normal
Mode
Sleep Command
Wake-Up From Interrupt
Timer Expire
SGn
Figure 5. Sleep Mode to Normal Mode Operation
.
Switch state change with
CS LOW generates INT
Switch state change with
CS LOW generates INT
INT
CS
Latch switch status
on falling edge of CS
SGn
Rising edge of CS does not
clear
INT
because state change
occurred while CS was LOW
Switch closed “1”
1
Switch
Status
Command
Switch open “0”
SGn Bit in SPI Word
1
Switch
Status
Command
0
Switch
Status
Command
0
Switch
Status
Command
1
Switch
Status
Command
0
Switch
Status
Command
Figure 6. Normal Mode Interrupt Operation
33972
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
