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MCZ33972EW 参数 Datasheet PDF下载

MCZ33972EW图片预览
型号: MCZ33972EW
PDF下载: 下载PDF文件 查看货源
内容描述: 多交换检测接口与抑制唤醒 [Multiple Switch Detection Interface with Suppressed Wake-Up]
分类和应用: 接口集成电路光电二极管
文件页数/大小: 32 页 / 1303 K
品牌: FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.1V
V
DD
5.25V, 8.0V
V
PWR
16V, -40°C
T
C
125°C, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with V
PWR
= 13V, T
A
= 25°C.
Characteristic
SWITCH INPUT
Pulse Wetting Current Time
Interrupt Delay Time
Normal Mode
Sleep Mode Switch Scan Time
Calibrated Scan Timer Accuracy
Sleep Mode
Calibrated Interrupt Timer Accuracy
Sleep Mode
DIGITAL INTERFACE TIMING
Required Low-state Duration on V
PWR
for Reset
V
PWR
0.2 V
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
Falling Edge of SCLK to Rising Edge of
CS
Required Setup Time
SI to Falling Edge of SCLK
Required Setup Time
Falling Edge of SCLK to SI
Required Hold Time
SI,
CS
, SCLK Signal Rise Time
SI,
CS
, SCLK Signal Fall Time
Time from Falling Edge of
CS
to SO Low-impedance
Time from Rising Edge of
CS
to SO High-impedance
Time from Rising Edge of SCLK to SO Data Valid
Notes
13.
14.
15.
16.
17.
18.
t
R (SI)
t
F (SI)
t
SO (EN)
t
SO (DIS)
t
VALID
t
SI (HOLD)
20
5.0
5.0
25
55
55
55
ns
ns
ns
ns
ns
t
SI (SU)
16
ns
t
LAG
50
ns
t
LEAD
100
ns
t
RESET
10
ns
μs
t
INT TIMER
10
t
SCAN
t
SCAN TIMER
10
%
t
PULSE (ON)
t
INT-DLY
100
5.0
200
16
300
μs
%
15
16
20
ms
μs
Symbol
Min
Typ
Max
Unit
These parameters are guaranteed by design. Production test equipment uses 4.16MHz, 5.0V SPI interface.
This parameter is guaranteed by design but not production tested.
Rise and Fall time of incoming SI,
CS
, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for valid output status data to be available on SO pin.
Time required for output states data to be terminated at SO pin.
Time required to obtain valid data out from SO following the rise of SCLK with 200pF load.
33972
8
Analog Integrated Circuit Device Data
Freescale Semiconductor