General
Table 3. Voltage and current operating behaviors (continued)
Symbol
R
PU
R
PD
Description
Internal pullup resistors
Internal pulldown resistors
Min.
20
20
Max.
50
50
Unit
kΩ
kΩ
Notes
1. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated
PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at V
DD
= 3.6 V
3. Measured at V
DD
supply voltage = V
DD
min and Vinput = V
SS
4. Measured at V
DD
supply voltage = V
DD
min and Vinput = V
DD
5.2.4 Power mode transition operating behaviors
All specifications except t
POR
and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• FEI clock mode
Table 4. Power mode transition operating behaviors
Symbol
t
POR
Description
After a POR event, amount of time from the point
V
DD
reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
• VLLS0
→
RUN
—
• VLLS1
→
RUN
—
• VLLS3
→
RUN
—
• LLS
→
RUN
—
• VLPS
→
RUN
—
• STOP
→
RUN
—
4
4.4
μs
4
4.4
μs
4
4.6
μs
42
53
μs
93
115
μs
95
115
μs
Min.
—
Typ.
—
Max.
300
Unit
μs
Notes
KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
13
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
