Clock Configuration Modes
Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=0)
1,2
(continued)
Mode
3
MODCK_H-
MODCK[1-3]
1011_100
1011_101
Bus Clock
(MHz)
Low
High
CPM Clock
(MHz)
Low
High
CPU Clock
(MHz)
Low
High
PCI Clock
(MHz)
Low
50.0
50.0
High
66.7
66.7
CPM
Multiplication
Factor
4
CPU
Multiplication
Factor
5
PCI
Division
Factor
6
80.0 106.7
80.0 106.7
2.5
2.5
200.0 266.6
200.0 266.6
4
4.5
320.0 426.6
360.0 480.0
4
4
1101_000
1101_001
1101_010
1101_011
1101_100
100.0 133.3
100.0 133.3
100.0 133.3
100.0 133.3
100.0 133.3
2.5
2.5
2.5
2.5
2.5
250.0 333.3
250.0 333.3
250.0 333.3
250.0 333.3
250.0 333.3
3
3.5
4
4.5
5
300.0 400.0
350.0 466.6
400.0 533.3
450.0 599.9
500.0 666.6
5
5
5
5
5
50.0
50.0
50.0
50.0
50.0
66.7
66.7
66.7
66.7
66.7
1101_101
1101_110
125.0 166.7
125.0 166.7
2
2
250.0 333.3
250.0 333.3
3
4
375.0 500.0
500.0 666.6
5
5
50.0
50.0
66.7
66.7
1110_000
1110_001
1110_010
1110_011
1110_100
100.0 133.3
100.0 133.3
100.0 133.3
100.0 133.3
100.0 133.3
3
3
3
3
3
300.0 400.0
300.0 400.0
300.0 400.0
300.0 400.0
300.0 400.0
3.5
4
4.5
5
5.5
350.0 466.6
400.0 533.3
450.0 599.9
500.0 666.6
550.0 733.3
6
6
6
6
6
50.0
50.0
50.0
50.0
50.0
66.7
66.7
66.7
66.7
66.7
1100_000
1100_001
1100_010
1
Reserved
Reserved
Reserved
2
3
4
5
6
The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a
table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed
the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature
devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz.
PCI_MODCK determines the PCI clock frequency range. SeeTable
for lower range configurations.
MODCK_H = hard reset configuration word [28–31] (see Section 5.4 in the SoC reference manual). MODCK[1-3] =
three hardware configuration pins.
CPM multiplication factor = CPM clock/bus clock
CPU multiplication factor = Core PLL multiplication factor
CPM_CLK/PCI_CLK ratio. When PCI_MODCK = 0, the ratio of CPM_CLK/PCI_CLK should be calculated from
SCCR[PCIDF] as follows:
CPM_CLK/PCI_CLK = (PCIDF + 1) / 2.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
31
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
